VHDL-FPGA-Verilog List Page 3541

VHDL-FPGA-Verilog list

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key44 Downloaded：0: 4* 4 keypad scanning process in the development of on-board VHDL debugging success, rest assured that the use of
Date : 2025-06-29 Size : 2kb User : 徐辉
mc8051_design Downloaded：0: MC8051 core , VHDL , Oregano Systems
Date : 2025-06-29 Size : 387kb User : jozo178
CRC_Generator Downloaded：0: This is a binary encoded on the check, by check, to verify whether the correct transmission
Date : 2025-06-29 Size : 5.04mb User : lee
quartus Downloaded：0: des algorithm send rx from serial port
Date : 2025-06-29 Size : 3.48mb User : mohamed
7 Downloaded：0: Seven-Segment LED display vhdl procedure on the experimental machine, and absolutely correct
Date : 2025-06-29 Size : 4kb User : weimin
1616 Downloaded：0: Vhdl language used to describe the 16* 16 dot matrix display alphabetical
Date : 2025-06-29 Size : 4kb User : weimin
fpgafifo Downloaded：0: Fpga-based FPGA-based realization of fifo asymmetrical design of synchronous FIFO
Date : 2025-06-29 Size : 9kb User : 沈
1 Downloaded：0: A very good VHDL Tutorial
Date : 2025-06-29 Size : 4.54mb User : 谢亮
modelsim Downloaded：0: very good！
Date : 2025-06-29 Size : 494kb User : 王海鹏
vhdl Downloaded：0: : A Shanghai taxi meter area for example, the use of Verilog HDL language taxi meter is designed so that it will have the time display, billing and simulated taxi start, stop, reset and other functions, and set up the dy
Date : 2025-06-29 Size : 207kb User : mindy
cordic-magnitude Downloaded：0: verilog code for magnitude cordic algrithm
Date : 2025-06-29 Size : 1kb User : meysam
shift_reg_sp Downloaded：0: serial to parrallel shift register
Date : 2025-06-29 Size : 1kb User : meysam

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