VHDL-FPGA-Verilog List Page 3509

VHDL-FPGA-Verilog list

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PS2-SPI Downloaded：0: Configuration software and its use SOPC approach to high-speed 12-bit serial AD7920 to achieve 0-3.3V the ADC conversion. PS2 controller interface module, the keyboard data is sent to the computer through the serial cons
Date : 2025-07-01 Size : 1kb User : 贺欧
VHDLjianpan Downloaded：0: VHDL design of a keyboard, and to tremble, to stability in the LED display. Procedures have been changed for the better, you can learn from you.
Date : 2025-07-01 Size : 964kb User : ywb
shuzipinlvjiVHDL Downloaded：0: Features: frequency meter. With four shows that will automatically count 7 the results of the metric system to automatically select a valid data - 4 high-dynamic show. Decimal point that is 1000, that is, KHz
Date : 2025-07-01 Size : 2kb User : ywb
vhdl_dds Downloaded：0: VHDL language using a simple DDS, easy to adjust the frequency and phase sine wave
Date : 2025-07-01 Size : 327kb User : dzt
fequency Downloaded：0: CPLD based on the number of degrees of accuracy, such as frequency meter, key peripheral functions can be achieved, frequency, phase, duty cycle measurement of parameters such as
Date : 2025-07-01 Size : 372kb User : dzt
dvf Downloaded：0: NC VHDL language use frequency, through the input frequency control word to adjust the frequency, the output of different frequency
Date : 2025-07-01 Size : 37kb User : dzt
std_31002lib Downloaded：0: library vhdl xst hdp src std 31002 dio components xhdp hdlib hdpdeps sub00 library vhdl xst hdp src std 31002 dio components xhdp hdlib hdpdeps sub00
Date : 2025-07-01 Size : 9kb User : A
guess_num Downloaded：0: a guess number game based on CPLD, include such functions as keyboard input, LCD display, voise output, and so on
Date : 2025-07-01 Size : 1.22mb User : jim
61EDA_D1116 Downloaded：0: A PLD Based Delta-Sigma DAC
Date : 2025-07-01 Size : 58kb User : 郭晨
DDSyuanma Downloaded：0: DDS Waveform Generator (Synplify pro compiler through)- the output frequency Fout = Fclk* 2 ^ M/2 ^ N- Resolution Fclk/2 ^ N- the maximum output frequency Fout = Fclk* 50 (theoretical value, the sampling theorem)
Date : 2025-07-01 Size : 298kb User : lishaozhe
Verilog_HDL Downloaded：0: Verilog_HDL
Date : 2025-07-01 Size : 257kb User : randy
dds Downloaded：0: The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Date : 2025-07-01 Size : 186kb User : 赵一

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