VHDL-FPGA-Verilog List Page 3447

VHDL-FPGA-Verilog list

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Mars-EP1C6-F_code2 Downloaded：0: The packet interface to FPGA board experimental procedure to study the source code, a total of 13 experimental procedure, there are 7-segment digital tube, 1602 LCD 12864 LCD, I2C bus, serial communication, DIP switch.
Date : 2025-07-22 Size : 4.42mb User : sunxh092
Mars-EP1C6-F_code3 Downloaded：0: This packet FPGA board to study a comprehensive experimental program source code, including two experiments: the traffic lights and digital clock.
Date : 2025-07-22 Size : 788kb User : sunxh092
LAB27 Downloaded：0: 1K points frequency FPGA-based modules, the clock signal input 24MHZ
Date : 2025-07-22 Size : 335kb User : 客家话
huawei_FPGA_design_flow Downloaded：0: fpga design flow of huawei
Date : 2025-07-22 Size : 32kb User : dongyuan
dds Downloaded：0: It is used inside the DSP BUILDER where ALTERA do DDS module, you can download a EP1C20400 through SIGNAL TAP-line testing.
Date : 2025-07-22 Size : 2.09mb User : ningning
decoder35 Downloaded：0: decoder verilog. it is a 3 t0 5 decoder that compile with modelsim.
Date : 2025-07-22 Size : 1kb User : MohammadReza
fir Downloaded：0: The use of VHDL language, designed a 11-order FIR filter. Easy to understand. .
Date : 2025-07-22 Size : 1kb User : 关小
exp3_BUTTON Downloaded：0: QUARTUS_NIOS ii interrupt the use of keys
Date : 2025-07-22 Size : 2.08mb User : 戚栋
VHDL Downloaded：0: 100 a simple VHDL example, you can refer to
Date : 2025-07-22 Size : 319kb User : 王子
fft Downloaded：0: filter
Date : 2025-07-22 Size : 556kb User : 陈丽华
micro Downloaded：0: 16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Date : 2025-07-22 Size : 30kb User : mojo
TLM-2.0.1 Downloaded：0: SystemC TLM 2.0.1 2009/7/15 latest source and documentation. -The latest system c TLM 2.0.1 7/15/2009 source code and documents
Date : 2025-07-22 Size : 11mb User : Archie

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