This packet FPGA board to study a comprehensive experimental program source code, including two experiments: the traffic lights and digital clock.

综合实验
........\交通灯
........\......\traffic
........\......\.......\cmp_state.ini
........\......\.......\db
........\......\.......\..\traffic.asm.qmsg
........\......\.......\..\traffic.cbx.xml
........\......\.......\..\traffic.cmp.cdb
........\......\.......\..\traffic.cmp.hdb
........\......\.......\..\traffic.cmp.qrpt
........\......\.......\..\traffic.cmp.rdb
........\......\.......\..\traffic.cmp.tdb
........\......\.......\..\traffic.cmp0.ddb
........\......\.......\..\traffic.dbp
........\......\.......\..\traffic.db_info
........\......\.......\..\traffic.eco.cdb
........\......\.......\..\traffic.fit.qmsg
........\......\.......\..\traffic.hier_info
........\......\.......\..\traffic.hif
........\......\.......\..\traffic.map.cdb
........\......\.......\..\traffic.map.hdb
........\......\.......\..\traffic.map.qmsg
........\......\.......\..\traffic.pre_map.cdb
........\......\.......\..\traffic.pre_map.hdb
........\......\.......\..\traffic.psp
........\......\.......\..\traffic.rtlv.hdb
........\......\.......\..\traffic.rtlv_sg.cdb
........\......\.......\..\traffic.rtlv_sg_swap.cdb
........\......\.......\..\traffic.sgdiff.cdb
........\......\.......\..\traffic.sgdiff.hdb
........\......\.......\..\traffic.signalprobe.cdb
........\......\.......\..\traffic.sld_design_entry.sci
........\......\.......\..\traffic.sld_design_entry_dsc.sci
........\......\.......\..\traffic.syn_hier_info
........\......\.......\..\traffic.tan.qmsg
........\......\.......\traffic.asm.rpt
........\......\.......\traffic.done
........\......\.......\traffic.fit.eqn
........\......\.......\traffic.fit.rpt
........\......\.......\traffic.fit.summary
........\......\.......\traffic.flow.rpt
........\......\.......\traffic.map.eqn
........\......\.......\traffic.map.rpt
........\......\.......\traffic.map.summary
........\......\.......\traffic.pin
........\......\.......\traffic.pof
........\......\.......\traffic.qpf
........\......\.......\traffic.qsf
........\......\.......\traffic.qws
........\......\.......\traffic.sof
........\......\.......\traffic.tan.rpt
........\......\.......\traffic.tan.summary
........\......\.......\traffic.vhd
........\......\.......\traffic_assignment_defaults.qdf
........\数字时钟
........\........\clock
........\........\.....\clock.asm.rpt
........\........\.....\clock.done
........\........\.....\clock.fit.eqn
........\........\.....\clock.fit.rpt
........\........\.....\clock.fit.summary
........\........\.....\clock.flow.rpt
........\........\.....\clock.map.eqn
........\........\.....\clock.map.rpt
........\........\.....\clock.map.summary
........\........\.....\clock.pin
........\........\.....\clock.pof
........\........\.....\clock.qpf
........\........\.....\clock.qsf
........\........\.....\clock.qws
........\........\.....\clock.tan.rpt
........\........\.....\clock.tan.summary
........\........\.....\clock.vhd
........\........\.....\cmp_state.ini
........\........\.....\db
........\........\.....\..\clock.asm.qmsg
........\........\.....\..\clock.cbx.xml
........\........\.....\..\clock.cmp.cdb
........\........\.....\..\clock.cmp.hdb
........\........\.....\..\clock.cmp.rdb
........\........\.....\..\clock.cmp.tdb
........\........\.....\..\clock.cmp0.ddb
........\........\.....\..\clock.db_info
........\........\.....\..\clock.eco.cdb
........\........\.....\..\clock.fit.qmsg
........\........\.....\..\clock.hier_info
........\........\.....\..\clock.hif
........\........\.....\..\clock.map.cdb
........\........\.....\..\clock.map.hdb
........\........\.....\..\clock.map.qmsg
........\........\.....\..\clock.pre_map.cdb
........\........\.....\..\clock.pre_map.hdb
........\........\.....\..\clock.psp
........\........\.....\..\clock.rtlv.hdb
........\........\.....\..\clock.rtlv_sg.cdb
........\........\.....\..\clock.rtlv_sg_swap.cdb
........\........\.....\..\clock.sgdiff.cdb
........\........\.....\..\clock.sgdiff.hdb
........\........\.....\..\clock.sld_design_entry.sci
........\........\.....\..\clock.sld_design_entry_dsc.sci

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