VHDL-FPGA-Verilog List Page 3405

VHDL-FPGA-Verilog list

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486bus Downloaded：0: This code implements the 486 bus functions, beginners can learn to learn
Date : 2025-07-13 Size : 4kb User : tom
outshiftreg Downloaded：0: This code implements the output shift register functions, beginners can learn to learn
Date : 2025-07-13 Size : 1kb User : tom
hello_led Downloaded：0: In the FPGA development board shows the string, using VHDL language, in a simple functional description FPGA-development process.
Date : 2025-07-13 Size : 6.97mb User : 韩飞
fulladder Downloaded：0: This code implements a full adder functions, for beginners to learn
Date : 2025-07-13 Size : 3kb User : tom
shuzizhong Downloaded：0: Then with the VHDL language multi-functional digital clock, with the normal timing functions, but also to the school, the school hours, and have the whole point timekeeping function of
Date : 2025-07-13 Size : 445kb User : 小黄
APB_I2S Downloaded：0: This is a Chinese version of the i2S bus, friends are engaged in the hardware would be helpful
Date : 2025-07-13 Size : 2kb User : 王涛
audio_codec Downloaded：0: i2s agreement, Philips developed specifically for the development of the audio protocol, which is its VHDL code, and want to help
Date : 2025-07-13 Size : 1.66mb User : 王涛
vhdlcpld Downloaded：0: Using vhdl implementation of four smart Responder, strong success, showing to answer in number. Out that no one answered, there is alarm.
Date : 2025-07-13 Size : 330kb User : bela
mc8051 Downloaded：0: Oregano Systems 8051 ip core
Date : 2025-07-13 Size : 385kb User : horven
shuizhongvhdl Downloaded：0: When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design
Date : 2025-07-13 Size : 1kb User : 小黄
counterfour Downloaded：0: verilog code for counter four
Date : 2025-07-13 Size : 1kb User : vmreddy
jiaotongdengsheji Downloaded：0: This is a traffic light control, VHDL program for maxplus platform, suitable for EDA Design
Date : 2025-07-13 Size : 142kb User : 小黄

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