VHDL-FPGA-Verilog List Page 3400

VHDL-FPGA-Verilog list

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power_gating Downloaded：0: ieee paper on power gating and can be use full for implementing on ip core
Date : 2025-07-13 Size : 958kb User : devil412
lamp_daisy090629 Downloaded：0: Altera company s FPGA using VHDL to the development, use quartus2 9.0 software EP1C3T144C8 Development Board to achieve ticker output.
Date : 2025-07-13 Size : 342kb User : Daisy
4x4Key_daisy090708 Downloaded：0: The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 the development board to realize 4x4 keyboard input control, and displayed in an eight-stage digital pipe.
Date : 2025-07-13 Size : 446kb User : Daisy
TrafficLights_daisy090701 Downloaded：0: The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board to realize a crossroads traffic lights control, including four traffic lights, and four 2-bit digital countdown devic
Date : 2025-07-13 Size : 539kb User : Daisy
fifo Downloaded：0: The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
Date : 2025-07-13 Size : 161kb User : Daisy
and_2 Downloaded：0: The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve an AND gate.
Date : 2025-07-13 Size : 167kb User : Daisy
ram Downloaded：0: The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a RAM memory.
Date : 2025-07-13 Size : 194kb User : Daisy
rom Downloaded：0: The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.
Date : 2025-07-13 Size : 175kb User : Daisy
signal_output Downloaded：0: The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
Date : 2025-07-13 Size : 1.11mb User : 蔡野锋
EDA Downloaded：0: eda
Date : 2025-07-13 Size : 179kb User : tom
shumaguan Downloaded：0: fpga under the seven-segment digital tube experiment reports that the University
Date : 2025-07-13 Size : 220kb User : tom
DDS Downloaded：0: This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continu
Date : 2025-07-13 Size : 473kb User : 蔡野锋

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