VHDL-FPGA-Verilog List Page 3343

VHDL-FPGA-Verilog list

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dff_clk Downloaded：0: A simple D flip-flop in Verilog description and simulation waveforms
Date : 2025-07-16 Size : 2kb User : 李慧静
dff_pre_clr Downloaded：0: Reset the D flip-flop with set of Verilog description and simulation waveforms.
Date : 2025-07-16 Size : 2kb User : 李慧静
graycnt_3 Downloaded：0: 3 Gray code counter verilog description and simulation waveforms
Date : 2025-07-16 Size : 2kb User : 李慧静
graycnt_14 Downloaded：0: 14-bit Gray code counter verilog description and simulation waveforms
Date : 2025-07-16 Size : 2kb User : 李慧静
timing_ctrl Downloaded：0: Receive timing controller verilog descriptions, and simulation waveforms.
Date : 2025-07-16 Size : 11kb User : 李慧静
div Downloaded：0: div dclk
Date : 2025-07-16 Size : 404kb User : 刘东鑫
Convolutionalencoder Downloaded：0: Application of VHDL language implementation of the convolutional encoder applications
Date : 2025-07-16 Size : 7kb User : zxy
Design_and_Analysis_of_Electronic_Code_Lock Downloaded：0: Design and Analysis of Electronic Code Lock
Date : 2025-07-16 Size : 864kb User : 钱阔
digitalsystemdesign Downloaded：0: FPGA designs are very classic PPT, Beihang XIA Yu-Wen teacher handouts
Date : 2025-07-16 Size : 1.02mb User : 张鹏
ethernet_tri_mode.tar Downloaded：0: Ethernet-based incentive program write verilog source code
Date : 2025-07-16 Size : 670kb User : 张鹏
freedev_i2c Downloaded：0: Prepared based on the Verilog source code for the sub-frequency circuits
Date : 2025-07-16 Size : 34kb User : 张鹏
123 Downloaded：0: easy
Date : 2025-07-16 Size : 261kb User : XC

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