VHDL-FPGA-Verilog List Page 3333

VHDL-FPGA-Verilog list

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i2c_wb_wrapper_latest.tar Downloaded：0: I2C+Wishbone in VHDL
Date : 2025-07-16 Size : 13kb User : mr_adam
prob2 Downloaded：0: SSTL
Date : 2025-07-16 Size : 1kb User : gao
prob1 Downloaded：0: UART
Date : 2025-07-16 Size : 1kb User : gao
pll Downloaded：0: Be able to run a phase-locked loop procedure is very good, can be used in many ways
Date : 2025-07-16 Size : 1kb User : 李俊
vhdl Downloaded：0: Experiment content, in order to validate memory memory works, need to use test case
Date : 2025-07-16 Size : 1kb User : 李明
oc_i2c_master Downloaded：0: I 2 C is a 2-line bidirectional serial interface, very suitable for chip-level communication. Because SOPC Builder does not provide I 2 C core, as described in this section I 2 C core is produced by Richard Herveille and
Date : 2025-07-16 Size : 254kb User : xuai
JPEG Downloaded：0: This paper describes the static image compression (JPEG) coding algorithm is the basic principle of compression process of the implementation process and its important discrete cosine transform (DCT) Algorithm theory and
Date : 2025-07-16 Size : 41kb User : xuai
COUNT Downloaded：0: This is a hexadecimal addition and subtraction counter source code, its change it can use other hex of the
Date : 2025-07-16 Size : 277kb User : max
shift_reg Downloaded：0: shift-reg
Date : 2025-07-16 Size : 1.29mb User : bxh
74hc4017 Downloaded：0: IC VHDL design
Date : 2025-07-16 Size : 689kb User : bxh
74HC151 Downloaded：0: IC VHDL design
Date : 2025-07-16 Size : 440kb User : bxh
74hc85 Downloaded：0: ＩＣ　VHDL design
Date : 2025-07-16 Size : 362kb User : bxh

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