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viterbi_for_bch
Downloaded:0
Viterbi based trellis decoder for (7,4)- binary BCH code
Date
: 2025-07-09
Size
: 1kb
User
:
shahifaqeer
RS_decoder
Downloaded:0
Reed solomon decoder based on table-lookup method VHDL code
Date
: 2025-07-09
Size
: 4kb
User
:
shahifaqeer
wtut_edif
Downloaded:0
Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
Date
: 2025-07-09
Size
: 20kb
User
:
shad
wtut_sc
Downloaded:0
DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock
Date
: 2025-07-09
Size
: 104kb
User
:
shad
wtut_ver
Downloaded:0
DCM supports two frequency modes for the DLL. By default, the DLL_FREQUENCY_MODE attribute is set to Low and the frequency of the clock signal at the CLKIN input must be in the Low (DLL_CLKIN_MIN_LF to DLL_CLKIN_MAX_LF)
Date
: 2025-07-09
Size
: 25kb
User
:
shad
wtut_vhd
Downloaded:1
When the DLL_FREQUENCY_MODE attribute is set to High, the frequency of the clock signal at the CLKIN input must be in the High (DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF) frequency range (MHz). See The Programmable Logic Data
Date
: 2025-07-09
Size
: 35kb
User
:
shad
DFNL
Downloaded:0
On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG connected to the CLKFB input of the DCM must be sourced from eith
Date
: 2025-07-09
Size
: 3kb
User
:
shad
rs2322
Downloaded:0
The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs (CLK
Date
: 2025-07-09
Size
: 1.54mb
User
:
shad
VHDL_flash
Downloaded:0
vhdl chip design a very good design
Date
: 2025-07-09
Size
: 4.6mb
User
:
Vampiro
VHDL_Codes
Downloaded:0
vhdl codes of basic components
Date
: 2025-07-09
Size
: 3.58mb
User
:
Vampiro
111
Downloaded:0
VeriloG HDL IS VEVRY USEFUL
Date
: 2025-07-09
Size
: 4kb
User
:
xinran
Shortest_job_first
Downloaded:0
shortest job first()
Date
: 2025-07-09
Size
: 365kb
User
:
qin yali
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