VHDL-FPGA-Verilog List Page 3306

VHDL-FPGA-Verilog list

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Audio_Out_Serializer Downloaded：0: The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Date : 2025-07-09 Size : 1kb User : gasha
cmd_pro Downloaded：0: Communications control part for the SD card send and receive part of the command, verilog language to describe the
Date : 2025-07-09 Size : 7kb User : 朱红梅
Avalon_Audio Downloaded：0: The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Date : 2025-07-09 Size : 2kb User : gasha
Clock_Edge Downloaded：0: The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Date : 2025-07-09 Size : 1kb User : gasha
SYNC_FIFO Downloaded：0: The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
Date : 2025-07-09 Size : 1kb User : gasha
data_pro Downloaded：0: SD cards for some of the data send and receive communication control part, verilog language to describe the
Date : 2025-07-09 Size : 9kb User : 朱红梅
yunlei Downloaded：0: Taxi billing system to achieve
Date : 2025-07-09 Size : 732kb User : lilei
color_conv Downloaded：0: BT656, YCBCR data format converted into VGA (888) data algorithm,
Date : 2025-07-09 Size : 1kb User : 朱红梅
i2c_master Downloaded：0: I2C controller, applied to a variety of I2C communication between master and slave devices
Date : 2025-07-09 Size : 5kb User : 朱红梅
ks_tree Downloaded：0: ks_tree
Date : 2025-07-09 Size : 4.35mb User : 李文民
Quartus Downloaded：0: Prepared using vhdl source signal generator can produce sine wave, you can also produce other waveforms as ne
Date : 2025-07-09 Size : 367kb User : LFwen
CU Downloaded：0: mips instruction controller.
Date : 2025-07-09 Size : 6kb User : dukenunee

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