VHDL-FPGA-Verilog List Page 3249

VHDL-FPGA-Verilog list

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UART_VHDL_Verilog_Lattice Downloaded：0: This compressed package contains serial process VHDL, Verilog, Lattice three versions of the code, have been achieved. In the compressed package, contains very detailed specifications of the serial implementation. Variou
Date : 2025-07-22 Size : 287kb User : shishu
ADC_AMP Downloaded：0: VHDL code for ADC on Spartan 3E starter kit
Date : 2025-07-22 Size : 2kb User : vuu
xb Downloaded：0: With the Hanning window design an FIR high-pass digital filter to meet the requirements the following parameters: passband edge frequency ωp = 0.7π, pass-band attenuation function αp = 0.4dB stop-band edge frequency Ωs =
Date : 2025-07-22 Size : 123kb User : xbwu1
frehp Downloaded：0: Based on the frequency sampling method to achieve type Ⅰ FIR digital high-pass filter
Date : 2025-07-22 Size : 1kb User : liguohong
VerilogExample Downloaded：0: verilog example
Date : 2025-07-22 Size : 111kb User : aa
uart Downloaded：0: FPGA in the UART modules, debugging through the Oh! ! We want to help, Hehe. . . I use the quartus7.2 version of the written, of course, also some copy online
Date : 2025-07-22 Size : 1.68mb User : 单子奇
add_16bits Downloaded：0: adder-19bts
Date : 2025-07-22 Size : 8kb User : 鍾潤宏
adder Downloaded：0: adder
Date : 2025-07-22 Size : 10kb User : 鍾潤宏
RA Downloaded：0: ripple adder
Date : 2025-07-22 Size : 2kb User : 鍾潤宏
for_ws Downloaded：0: full adder ,rippple adder
Date : 2025-07-22 Size : 5kb User : 鍾潤宏
divtest Downloaded：0: fenpinqi
Date : 2025-07-22 Size : 32kb User : 张宁
an484_CN Downloaded：0: With the MAX II CPLD, achieved through the SMBus pin GPIO expansion
Date : 2025-07-22 Size : 220kb User : loge

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