VHDL-FPGA-Verilog List Page 3233

VHDL-FPGA-Verilog list

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Verilog-HDL Downloaded：0: Verilog-HDL Practice and Application System Design
Date : 2025-07-23 Size : 14.72mb User : 李秀艳
7seg-led Downloaded：0: The Lantern VHDL program, containing the digital pipe and led lights are displayed, according to a variety of recycling methods show once again that
Date : 2025-07-23 Size : 17kb User : liwx
frequency_meter Downloaded：0: Simple frequency meter, to test pulses between 0 ~ 10000KHz signal frequency and displays in the digital pipe. Use 100KHz pulse as a reference signal. Includes curriculum design report.
Date : 2025-07-23 Size : 12kb User : 石帆
cordic_lattice Downloaded：0: lattice implementation of pot with cordic algorithm
Date : 2025-07-23 Size : 559kb User : park sang yoon
bch Downloaded：0: Experimental report VHDL VHDL verilog rs flip-flop experiment experimental report VHDL VHDL verilog rs flip-flop experiment
Date : 2025-07-23 Size : 15kb User : santhu
dac8143 Downloaded：0: Digital to Analog Converter Model for Analog Devices part DAC 8143.
Date : 2025-07-23 Size : 1kb User : salman
ads7809 Downloaded：0: VHDL model file for Analog devices Analog to Digital converter model ADC7809.
Date : 2025-07-23 Size : 1kb User : salman
fifo64x8_tb Downloaded：0: Testbench for Xilinx 64x8 FIFO.
Date : 2025-07-23 Size : 1kb User : salman
TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA Downloaded：0: Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection
Date : 2025-07-23 Size : 27.09mb User : ramanaidu
demux Downloaded：0: In contrast with the multiplexer function can be a bit of information on the allocation of the output by selecting one of them.
Date : 2025-07-23 Size : 1kb User : 李宗晟
CPLD Downloaded：0: Tetris with vga display based on the fpga, but not a true game Tetris
Date : 2025-07-23 Size : 2.2mb User : 万小中
shouhuoji Downloaded：0: Automatic vending machines with the Verilog language, along with realization of courseware
Date : 2025-07-23 Size : 649kb User : 万小中

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