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VHDL-FPGA-Verilog list
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USED TO CALCULATE DELAY
Date : 2025-07-24 Size : 3kb User : praba

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vhdl code for fir filter
Date : 2025-07-24 Size : 1kb User : praba

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Used to truncate the input signal
Date : 2025-07-24 Size : 1kb User : praba

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VHDL CODE FOR RAM AND ROM
Date : 2025-07-24 Size : 1kb User : praba

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vhdl CODE FOR moore MODEL AND mux
Date : 2025-07-24 Size : 1kb User : praba

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FPGA PWM control and VGA display use VHDL language with simulation.
Date : 2025-07-24 Size : 302kb User : xiaominjin

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a VHDL source code on HDB3 encoder realaized in FPGA/CPLD
Date : 2025-07-24 Size : 1kb User : xiaominjin

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press scan and LED display
Date : 2025-07-24 Size : 265kb User : jiehao

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PS2 based on verilog language interface and RS232 interface implementation
Date : 2025-07-24 Size : 1.67mb User : jiehao

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1. The source file in src directory, QII project file saved in Proj directory 2. Program implementation function is to display color VGA display stripes, a total of eight kinds of colors, you can use the embedded logic a
Date : 2025-07-24 Size : 3.98mb User : jiehao

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Verilog language stepper motor control program, the control signals dir, pul, ena,
Date : 2025-07-24 Size : 382kb User : jiehao

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tlv5620 chip Verilog language DAC conversion code
Date : 2025-07-24 Size : 286kb User : jiehao
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