VHDL-FPGA-Verilog List Page 3167

VHDL-FPGA-Verilog list

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DDS Downloaded：0: vhdl prepared dds signal generator which is a more ancient writing, but it is simple
Date : 2025-07-29 Size : 225kb User : deyi
CycloneII_NiosII_2C35_Rev02_DB_SCH Downloaded：0: nios development board circuit CycloneII_NiosII_2C35_Rev02_DB_SCH.zip
Date : 2025-07-29 Size : 762kb User : dengfengjun
decoder38 Downloaded：0: vhdl decoder written 38 full document, open the can
Date : 2025-07-29 Size : 163kb User : deyi
gate Downloaded：0: vhdl programs written in the logic gate circuit suitable for beginners, very simple
Date : 2025-07-29 Size : 140kb User : deyi
VHDL-clock Downloaded：0: for vhdl！！
Date : 2025-07-29 Size : 1.13mb User : 李鸿章
key_led Downloaded：0: Simple calculator keyboard and LED display, very simple, but can also be said very complicated
Date : 2025-07-29 Size : 509kb User : ultraman
counter_8050 Downloaded：0: The function of this experiment as follows: 10 binary counters from 80-50, 2 times/sec, where clk is 50MHZ, second function of a need for external divider
Date : 2025-07-29 Size : 434kb User : 谢维磊
waterled_2group Downloaded：0: LED0- LED11, from the beginning of the loop LED0 LED1 light, two lights as a group, every 1 second for a group of lights, where the clock used for 50MHZ, plus a divider so the need for frequency division
Date : 2025-07-29 Size : 383kb User : 谢维磊
waterled Downloaded：0: LED3- LED10, from the beginning of the loop LED10 bright lights for every one from another, according to SW1 to stop beating, and then click on the continue beating again
Date : 2025-07-29 Size : 372kb User : 谢维磊
HEX_1F Downloaded：0: The function of this experiment as follows: with each passing second, cathodic evolution of the digital control loop from 0 to F
Date : 2025-07-29 Size : 429kb User : 谢维磊
reed_eeprom Downloaded：0: This code read EEPROM I2C (for NIOS2).
Date : 2025-07-29 Size : 7kb User : sergey
irq Downloaded：0: Universal Initiolizator processings of interruptions (for NIOS2)
Date : 2025-07-29 Size : 2kb User : sergey

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