VHDL-FPGA-Verilog List Page 3162

VHDL-FPGA-Verilog list

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FSK_demodulation_VHDL Downloaded：0: VHDL-based FSK demodulation process, a detailed explanatory notes, and attached in the final simulation map, easy to understand and verify.
Date : 2025-07-29 Size : 33kb User : kuaile
URAT_transmitter_receiver_VHDL Downloaded：0: UART in VHDL-based procedures, including the top-level procedures, procedures for the baud rate generator, UART transmitter program, UART receiver program four part of the program. Detailed notes, and attached to each pr
Date : 2025-07-29 Size : 36kb User : kuaile
PLCC84_Socket_mdy Downloaded：0: PLCC84 socket package, for example, and so on cpld chip EPM7128slc84
Date : 2025-07-29 Size : 4kb User : xue_1986
mail2xilinx Downloaded：0: sysgen example for FFT application
Date : 2025-07-29 Size : 1.12mb User : bala
dwt2d_latest[1].tar Downloaded：0: code of dwt
Date : 2025-07-29 Size : 404kb User : 陈先生
matrixkeyscan Downloaded：0: 4* 4 matrix keyboard VHDL control statements, I have written, easy to understand, you can reference to see if someone need
Date : 2025-07-29 Size : 117kb User : 无真实
QuartusIIIntroduction Downloaded：0: About QuartusII
Date : 2025-07-29 Size : 3.95mb User : 冯侃
ex1.v Downloaded：0: 4-bit full adder implemented with Verilog HDL
Date : 2025-07-29 Size : 1kb User : gb18030
VHDL(LOCK) Downloaded：0: VHDL Digital Design and Implementation of lock 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning digital code lock design 2. Experimental content Design a digital lock on thei
Date : 2025-07-29 Size : 18kb User : 爱好
VHDL(sin) Downloaded：0: ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generat
Date : 2025-07-29 Size : 17kb User : 爱好
VHDLtest Downloaded：0: Sequence Detector Design 1. Purpose of the experiment 1. Control with VHDL state machine approach to achieve 2. Using the state machine to design a sequence detector 2. Experimental content Using the state machine to des
Date : 2025-07-29 Size : 86kb User : 爱好
VHDLdigital Downloaded：0: 7 digital control design and implementation of the decoder 1. Purpose of the experiment 1. To master digital control decoder 7 Design and Implementation 2. Master modular design 2. Experimental content Design of a 7-segm
Date : 2025-07-29 Size : 87kb User : 爱好

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