VHDL-FPGA-Verilog List Page 3117

VHDL-FPGA-Verilog list

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yuanma1 Downloaded：0: Taxi meter design source code, very useful oh. Hope to share with everyone the next.
Date : 2025-08-03 Size : 7kb User : 黎明毅辉
yuanma Downloaded：0: Taxi meter source code, very good, has been compile, entirely correct.
Date : 2025-08-03 Size : 6kb User : 黎明毅辉
NIOSII_LED Downloaded：0: Done in the FPGA development board based on Altera Corporation NiosII soft-core processor running water light test
Date : 2025-08-03 Size : 4.54mb User : 赵静
Sdram_Control_2Port Downloaded：0: Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language.
Date : 2025-08-03 Size : 11kb User :
serial Downloaded：0: Verilog language through the serial communication program, has compression, no password
Date : 2025-08-03 Size : 69kb User : 天良
lcd_1602_v Downloaded：0: In quartus environment, through the verilog language lcd1602 display program
Date : 2025-08-03 Size : 348kb User : 天良
PS_2_v Downloaded：0: In quartus 2 environment, through the mouth of VHDL programming language PS_2 and compiled successfully.
Date : 2025-08-03 Size : 299kb User : 天良
key_led_v Downloaded：0: In quartus 2 environment, based on verilog language button _LED light off function, and compile, for beginners.
Date : 2025-08-03 Size : 238kb User : 天良
FPGA-clock Downloaded：0: VHDL-based clock design (de2 development platform), contains the source code, simulation charts of each module, structure diagram, and the mission report. For reference study.
Date : 2025-08-03 Size : 3.4mb User : Bertrand
additionneurcomplet Downloaded：0: additionneur complet
Date : 2025-08-03 Size : 20kb User : jihed
FPGA_EP2C5 Downloaded：0: miniFPGA,learn fpga chark info
Date : 2025-08-03 Size : 82kb User : roccon
wave_gen Downloaded：0: wave generator in vhdl
Date : 2025-08-03 Size : 10kb User : k

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