VHDL-FPGA-Verilog List Page 3101

VHDL-FPGA-Verilog list

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pll Downloaded：0: DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, synchronous detection circuit established, constitute a model N divider. The whole system of the center frequency (ie signal
Date : 2025-11-15 Size : 1kb User : 鬼舞十七
FPGA_UART Downloaded：0: FPGA serial interface. Send and receive data function code
Date : 2025-11-15 Size : 9kb User : lichenlin
74HC164 Downloaded：0: 74HC164 microcontroller and digital control applications, 0 ~ F automatic display
Date : 2025-11-15 Size : 40kb User :
fft Downloaded：0: FFT code, and guidance to achieve the text, language is VHDL
Date : 2025-11-15 Size : 382kb User : shibin
SRAM_16Bit_512K Downloaded：0: Written in VHDL SRAM control procedures, the development board verified.
Date : 2025-11-15 Size : 11kb User : 王志慧
an501_design_example Downloaded：0: In the MAX2 series CPLD to realize pulse width modulation (PWM), a complete design and simulation results into the program.
Date : 2025-11-15 Size : 253kb User : 王志慧
UARTVHDL Downloaded：0: UART is a widely used serial data communication circuit. The design includes UART transmitter, receiver and baud rate generator. Application of EDA design technology based on FPGA/CPLD device design and implementation of
Date : 2025-11-15 Size : 236kb User : 王志慧
DE2_NET Downloaded：0: document is waveform file testing for any RLE encoder
Date : 2025-11-15 Size : 3kb User : ren
MCU8951 Downloaded：1: The document is embedded in the FPGA design system of a microcontroller core, and has 51 nuclear source code written in VHDL.
Date : 2025-11-15 Size : 4.58mb User : 萧天
8b Downloaded：0: This is tftlcd a test program, on the SPFD5240A, and thank you for support
Date : 2025-11-15 Size : 3kb User : 沈
RGMII_video_shiftregs Downloaded：0: By verilog programming, high-speed video using rgmii interface signal transmission.
Date : 2025-11-15 Size : 1kb User : steven
SpeechClock Downloaded：0: SpeechClock
Date : 2025-11-15 Size : 297kb User : 123

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