VHDL-FPGA-Verilog List Page 3091

VHDL-FPGA-Verilog list

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uart Downloaded：0: Prepared based on verilog HDL uart serial communication interface program
Date : 2025-11-15 Size : 920kb User : 张建
freq Downloaded：0: VHDL, design low frequency digital frequency meter, select the frequency method to program, mainly the control circuit, produced by the gate and the latch so clear signal.
Date : 2025-11-15 Size : 429kb User : 付晓
MultifunctionDigitalClock Downloaded：0: quartus software environment using verilog language multifunction digital clock
Date : 2025-11-15 Size : 241kb User : 张建
zhjta Downloaded：0: Five households in the design of a lift, the lift must meet the general function of each layer can be upstairs or downstairs of their choice to do
Date : 2025-11-15 Size : 3kb User : 文涛
cpu Downloaded：0: The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. Fo
Date : 2025-11-15 Size : 2.09mb User : mollyma
ditietickets Downloaded：0: Using VHDL language metro ticket system. Ticketing system automatically calculated according to the number of fares via station
Date : 2025-11-15 Size : 211kb User : mollyma
electricwatch Downloaded：0: VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions
Date : 2025-11-15 Size : 952kb User : mollyma
FPGA1IIR4 Downloaded：0: About iir introduction, hope we can together. Filter learning for understanding and study of this useful, detailed information on features
Date : 2025-11-15 Size : 316kb User : 董军
cpu_lecture_latest.tar Downloaded：0: Simple AVR implementation in VHDL. Synthetyisable design.
Date : 2025-11-15 Size : 1.9mb User : sza2
NIOS_lcd12864 Downloaded：0: 12864LCD NIOS II system based on reading and writing.
Date : 2025-11-15 Size : 8.75mb User : wlq
BER_examination Downloaded：0: FPGA-based pseudo-random sequence of bit error rate testing, including the occurrence of random sequence, random sequence to receive statistics.
Date : 2025-11-15 Size : 488kb User : wlq
FPGA_fenpin Downloaded：0: Using FPGA to build a 1:1 divider, you can change the frequency slightly modified controllable duty cycle controlled by the clock output.
Date : 2025-11-15 Size : 2.66mb User : wlq

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