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VHDL-FPGA-Verilog list
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DESCRIPTION : Demultiplexer -- Width: 8 -- Number of terminals: 4 -- Output enable active: HIGH -- Output active : HIGH
Date : 2025-11-17 Size : 1kb User : 王想

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shifter
Date : 2025-11-17 Size : 143kb User : Saint Zhang

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sin_gnt
Date : 2025-11-17 Size : 913kb User : Saint Zhang

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adder
Date : 2025-11-17 Size : 392kb User : Saint Zhang

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Achieve UART transmit function, using the state machine to describe its function.
Date : 2025-11-17 Size : 1kb User : liu weiwei

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To achieve the desired music to be based at89s51 keyboard microcontroller design!
Date : 2025-11-17 Size : 276kb User : 唐一峰

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UART VHDL component
Date : 2025-11-17 Size : 2kb User : Dmitry

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CRC16 VHDL component implements sequential algorithm for incoming data CRC16 calculation
Date : 2025-11-17 Size : 3kb User : Dmitry

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XILINX BEGINNERS BOOK
Date : 2025-11-17 Size : 5.95mb User : sy

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adder加法器 將A+B16BITS 相加 請多多利用
Date : 2025-11-17 Size : 332kb User : 王正皇

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Introduction to learning verilog code, ensure that you will use VERIOLG a look
Date : 2025-11-17 Size : 156kb User : lys

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dds files generated source code, useful, called IP cores, can be used in the ISE
Date : 2025-11-17 Size : 2kb User : wz
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