VHDL-FPGA-Verilog List Page 306

VHDL-FPGA-Verilog list

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QPSK_v Downloaded：0: 1-bit QPSK code for verilog.
Date : 2025-12-30 Size : 100kb User : Kashif
DIGITAL-PID Downloaded：0: Use verilog language design DIGITAL-PID source
Date : 2025-12-30 Size : 1010kb User : 磊
20161227_sf Downloaded：0: AES encryption algorithm in the FPGA column hybrid module implementation source code, using language Verillog integrated in the Quartus II software
Date : 2025-12-30 Size : 129kb User : 柳广兴
20161122_ff Downloaded：0: MD5 authentication part of the first round contains an F function of the operation of the FPGA implementation of the source code, using Verilog, integrated in the Quartus
Date : 2025-12-30 Size : 319kb User : 柳广兴
20161122_gg Downloaded：0: FPGA contains one operation in the second round of the G function MD5 authentication component implementation source code, using Verilog, synthesis in Quartus
Date : 2025-12-30 Size : 314kb User : 柳广兴
20161203_hh Downloaded：0: FPGA third round included H functions in one operation MD5 authentication component implementation source code, using Verilog, synthesis in Quartus
Date : 2025-12-30 Size : 289kb User : 柳广兴
20161203_ii Downloaded：0: The fourth round MD5 authentication section contains FPGA one operation I Functions of the source code, using Verilog, synthesis in Quartus
Date : 2025-12-30 Size : 301kb User : 柳广兴
TEST1 Downloaded：0: In this experiment, three button switches to represent three input a full adder (Ai, Bi, Ci) two by two LED to indicate output a full adder (Si, C). By entering different values and observe the results entered a full-add
Date : 2025-12-30 Size : 273kb User : 小方
test2 Downloaded：0: 1, different statements are described in VHDL language task selector, and distinguished by comparing different statements compiled simulation described. 2, and verify the results through hardware simulation download.
Date : 2025-12-30 Size : 876kb User : 小方
test3 Downloaded：0: The experiment task is to use Quartus II software, text input, generates a basic flip-flop, flip-flop may be a form, you can also structure NAND gate NOR gate structure. Use the key experiment using key module 7 and 8 ke
Date : 2025-12-30 Size : 223kb User : 小方
test4 Downloaded：0: This experiment requires the completion of a two-decimal counter and through digital static display. In the experiment, the system clock is selected as the input clock (clk) ,, two key input, key 8 when high, reset, when
Date : 2025-12-30 Size : 266kb User : 小方
test5 Downloaded：0: The experiment required to complete the task in the role of the clock signal through the input keys displays the corresponding key on the digital tube. In the experiment, the digital clock as scan clock 1KHZ with four to
Date : 2025-12-30 Size : 358kb User : 小方

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