VHDL-FPGA-Verilog List Page 293

VHDL-FPGA-Verilog list

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FPGA-for-UART-source-code Downloaded：0: Verilog source code for UART interface communication FPGA, including serial read and serial write module
Date : 2025-06-02 Size : 169kb User : 王大锤
FPGA-VGA-interface-code Downloaded：0: Verilog source code for communication VGA interface communication, including VGA line scan and frame scan module
Date : 2025-06-02 Size : 501kb User : 王大锤
BUJINDIANJI Downloaded：0: Considering the resources of the microcontroller and the actual work needs, it is necessary to complete the maximum speed start and accelerate the whole process in the 255 acceleration steps, and when the actual required
Date : 2025-06-02 Size : 10.8mb User : 申彦磊
UART Downloaded：0: Perfectly realize serial communication between FPGA and PC (8 message transmission only)
Date : 2025-06-02 Size : 3.14mb User : 赵嘉楠
PC_FPGA_Communication Downloaded：0: This software uses serial port to realize the communication between computer and FPGA. Using vhdl. this is the basic software to develop the FPGA.
Date : 2025-06-02 Size : 1.44mb User : kc218
board Downloaded：0: 4 led lights change 0000 to 1111 in binary, then change 1111 to 0000, plus temperature measurement
Date : 2025-06-02 Size : 3.29mb User : 张小二
pluse_count Downloaded：0: To take advantage of the FPGA system clock frequency division for timer configuration and operation regularly
Date : 2025-06-02 Size : 1kb User : KO
freq_100M Downloaded：0: On the FPGA platform, verilog, frequency measurement, debugged, can be opened on quartus.
Date : 2025-06-02 Size : 14.93mb User : 秦枫
m-Sequence Downloaded：0: FPGA, verilog, output M sequence, has been successfully debugged, can be opened directly on the Quartus.
Date : 2025-06-02 Size : 4.88mb User : 秦枫
phase_move Downloaded：0: FPGA platform, ve has been debugged, verilog language, to achieve the shift to the waveform, the module.
Date : 2025-06-02 Size : 2kb User : 秦枫
DDR_TEST Downloaded：0: Based on xc65slx16 ise 14.7 DDR3 test template, validated and can be used for reference in the fpga development study, also can be used as a template development.
Date : 2025-06-02 Size : 6.58mb User : 陈传开
watch_dog Downloaded：0: Based on EPM1270F256 4 road guard dog control logic, to realize the function of filtering, time delay and reset.
Date : 2025-06-02 Size : 383kb User : 陈传开

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