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VHDL-FPGA-Verilog list
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firmware for Onida TV
Date : 2025-11-19 Size : 8kb User : RajeshSharma

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Huawei internal information, useful and detailed on the FPGA development process and details
Date : 2025-11-19 Size : 32kb User : 恋可可西里

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Reed-solomon decoder, encoder design note
Date : 2025-11-19 Size : 883kb User : Seok Hoon Shin

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Image processing on FPGA has a strong reference to the papers of a good reference for beginners value
Date : 2025-11-19 Size : 138kb User : gdr

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VHDL-based digital clock design, this paper presents a detailed code, directly available!
Date : 2025-11-19 Size : 1kb User : 马聪聪

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The Altera(R) RTP Receiver function implements a buffer for received RTP packets. Duplicated and re-ordered packets are corrected. Missing packets can be fixed using Pro-MPEG Code of Practice #3 Forward Error Correction
Date : 2025-11-19 Size : 2.31mb User : Seok Hoon Shin

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The Altera(R) UDP/IP function implements a hardware solution for the transmission and reception of UDP/IP encapsulated network traffic.
Date : 2025-11-19 Size : 725kb User : Seok Hoon Shin

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It is a VHDL program on FPGA controling RS232 ,and it can receive and transmit data normally.
Date : 2025-11-19 Size : 5kb User : dujuan

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a verilog program on FPGA to control LCD.
Date : 2025-11-19 Size : 4kb User : dujuan

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A usefull book for veriog learners.
Date : 2025-11-19 Size : 3.98mb User : dujuan

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a veriog program completed on FPGA to contrlo a uart to communicaton with a computer
Date : 2025-11-19 Size : 1kb User : dujuan

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Verilog HDL language, easy to understand tutorials, Xia Wenyu the second edition.
Date : 2025-11-19 Size : 11.55mb User : 文超
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