VHDL-FPGA-Verilog List Page 2906

VHDL-FPGA-Verilog list

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RAM2x64C_1 Downloaded：0: Dual-port RAM for data storage and reading, in the FFT processor heavy, fast read and store data, can improve the processor speed
Date : 2025-11-19 Size : 2kb User : 姚兴波
NIOSIIbased_digitalClock Downloaded：0: SOPC an instance has been proven to facilitate people who are learning to use as a routine.
Date : 2025-11-19 Size : 415kb User : zhubeibei
Altera_knowledge Downloaded：0: FPGA design guidelines, on the FPGA design a very interesting document, it describes the image of the design of some of the key
Date : 2025-11-19 Size : 1.55mb User : liangxiao
vga Downloaded：0: FPGA systems through control of the computer monitor by the VGA interface to display bar, vertical bar and board graphics
Date : 2025-11-19 Size : 347kb User : 大机子
nios_uart Downloaded：0: nios uart
Date : 2025-11-19 Size : 18.19mb User : 刘宏
SPI Downloaded：0: design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed
Date : 2025-11-19 Size : 1kb User : weichenghao
xsoc-beta-093 Downloaded：0: a processor source code and simple system-on-a-chip !
Date : 2025-11-19 Size : 3.19mb User : yangxf
Gap_Finder Downloaded：0: To find the distance between two input 4 bits and output it in 2 bits
Date : 2025-11-19 Size : 1kb User : chenghao wei
DX-PHY Downloaded：0: ddr phy design spec and example!!
Date : 2025-11-19 Size : 245kb User : yangxf
MIPS1CYCLE Downloaded：0: a. Load the data stored in the X and Y locations of the data memory into the X and Y registers. b. Add the X and Y registers and store the result in the Z register. c. Store the data from the Z register into the Z memory
Date : 2025-11-19 Size : 2kb User : chenghao wei
DE2_Default Downloaded：0: basic
Date : 2025-11-19 Size : 3.73mb User : 鲁金屏
sevenlight Downloaded：0: seven
Date : 2025-11-19 Size : 815kb User : 鲁金屏

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