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VHDL-FPGA-Verilog list
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Lab17 sinusoidal signal generator
Date : 2025-11-20 Size : 170kb User : 廖杰

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A cross-clock domain clock synchronization methods, including the source files and test files ~
Date : 2025-11-20 Size : 1kb User : 崔亮

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When receiving a signal (D_start), the start time, and then received another signal (D_stop), the time the end of time by time A, then the time A and B compare a given time, if less than the time B, end of the process, p
Date : 2025-11-20 Size : 5kb User : Devine

This is a paper on the FPGA hardware design, the main discussion is based on FPGA for Portable Vibration Spectrum Analyzer, personal feeling of great value
Date : 2025-11-20 Size : 1.9mb User : 安培

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Sample code of "Those things regarding to NIOSII rev6.0"
Date : 2025-11-20 Size : 13.23mb User : 卢德容

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Based on the design of nios lanterns, DE0 Development Board on the flow, racing lights
Date : 2025-11-20 Size : 7.51mb User : 朱欢

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Vhdl implementation with shaking and the use of key consumer written pwm vhdl
Date : 2025-11-20 Size : 1kb User : 王正

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i2c module
Date : 2025-11-20 Size : 3kb User : meiqiling

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Digital frequency meter FPGA code with verilog language.
Date : 2025-11-20 Size : 425kb User : 郭志东

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sinewave
Date : 2025-11-20 Size : 4.06mb User : 姜国千

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mcode_FPGA
Date : 2025-11-20 Size : 1.23mb User : 姜国千

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FPGA_RS_232
Date : 2025-11-20 Size : 468kb User : 姜国千
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