VHDL-FPGA-Verilog List Page 2867

VHDL-FPGA-Verilog list

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RCII-CY1C12_exampla Downloaded：0: cyclone2 board cd
Date : 2025-11-20 Size : 50.47mb User : pla
miniuart2 Downloaded：0: This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a PC fo
Date : 2025-11-20 Size : 2.47mb User : 李涛
SampleEngine Downloaded：0: source code of sample program
Date : 2025-11-20 Size : 21kb User : rajesh
Pentek.Sum06 Downloaded：0: Pentek dociment about FPGA Radars
Date : 2025-11-20 Size : 686kb User : abensrhir
FT2232H_USB_Core Downloaded：0: The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieved. The core ha
Date : 2025-11-20 Size : 6kb User : 李涛
13 Downloaded：0: What causes the risk? Bank accounting to professional risk prevention?
Date : 2025-11-20 Size : 753kb User : jiajia
cpu01 Downloaded：0: cpu 16 bit fpga vhdl
Date : 2025-11-20 Size : 413kb User : sdy
12dac Downloaded：0: a 12bit dac need a lpf which can view clearly
Date : 2025-11-20 Size : 1kb User : 王鹏
vhdl-led Downloaded：0: base on vhdl design a led chinese-rolled monitor
Date : 2025-11-20 Size : 2.4mb User : 王鹏
squart Downloaded：0: a squart-singnal production is discribed by vhdl
Date : 2025-11-20 Size : 494kb User : 王鹏
123 Downloaded：0: mutiple signal productions vhdl
Date : 2025-11-20 Size : 60kb User : 王鹏
bijiaoqi Downloaded：0: compare by vhdl ,use as changing sin to squart signal
Date : 2025-11-20 Size : 4.69mb User : 王鹏

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