cpu 16 bit fpga vhdl

cpu01\cpu.prj
.....\cpu.stx
.....\cpu.xst
.....\cpu01.ise
.....\cpu01.ise_ISE_Backup
.....\cpu01.vhd
.....\cpu01tb.ant
.....\cpu01tb.jhd
.....\cpu01tb.tbw
.....\cpu01tb.vhw
.....\cpu01tb.xwv
.....\cpu01tb.xwv_bak
.....\cpu01tb2.ant
.....\cpu01tb2.jhd
.....\cpu01tb2.tbw
.....\cpu01tb2.vhw
.....\cpu01tb2.xwv
.....\cpu01tb2.xwv_bak
.....\cpu01tb2_bencher.prj
.....\cpu01tb3.ant
.....\cpu01tb3.jhd
.....\cpu01tb3.tbw
.....\cpu01tb3.vhw
.....\cpu01tb3.xwv
.....\cpu01tb3.xwv_bak
.....\cpu01tb3_bencher.prj
.....\cpu01tb_bencher.prj
.....\cpu_vhdl.prj
.....\pepExtractor.prj
.....\prjname.lso
.....\ram.prj
.....\ram.stx
.....\ram.xst
.....\ram_vhdl.prj
.....\top.cmd_log
.....\top.lso
.....\top.ngr
.....\top.prj
.....\top.syr
.....\top.xst
.....\top_summary.html
.....\xst\work\hdllib.ref
.....\...\....\hdpdeps.ref
.....\...\....\sub00\vhpl00.vho
.....\...\....\.....\vhpl01.vho
.....\...\....\.....\vhpl02.vho
.....\...\....\.....\vhpl03.vho
.....\...\....\.....\vhpl04.vho
.....\...\....\.....\vhpl05.vho
.....\...\....\.....\vhpl06.vho
.....\_xmsgs\xst.xmsgs
.....\__ISE_repository_cpu01.ise_.lock
.....\xst\dump.xst\top.prj\ngx\notopt
.....\...\........\.......\...\opt
.....\...\........\.......\ngx
.....\...\........\top.prj
.....\...\work\sub00
.....\...\dump.xst
.....\...\projnav.tmp
.....\...\work
.....\xst
.....\_xmsgs
cpu01

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