VHDL-FPGA-Verilog List Page 2853

VHDL-FPGA-Verilog list

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sdram_controller_latest.tar Downloaded：0: sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.
Date : 2025-11-20 Size : 30kb User : Andrei
wb_async_mem_bridge_latest.tar Downloaded：0: wb_async_mem_bridge_latest.tar.gz- it is controller without independents sources clock . Only write or read case synchronization for WB controller interface bus.(computable with WB interface protocol).
Date : 2025-11-20 Size : 72kb User : rozenan
zbt_sram_controller_latest.tar Downloaded：0: zbt_sram_controller_latest.tar.gz- pipeline “ NO WAIT” state bus SRAM model.
Date : 2025-11-20 Size : 386kb User : rozenan
jk Downloaded：0: Trigger for example, JK flip-flop of VHDL implementation
Date : 2025-11-20 Size : 285kb User : 宋茜
comparator_4 Downloaded：0: VHDL-based numerical comparator, the comparator through the implementation of this idea can be extended to more places
Date : 2025-11-20 Size : 272kb User : 宋茜
mux4 Downloaded：0: VHDL-based implementation of the four adder, through the design of this adder, can be extended to more bits Adder
Date : 2025-11-20 Size : 265kb User : 宋茜
ADC Downloaded：0: ACTEL FUSION STARTKIT FPGA development board routines, to achieve 16-channel control of adc adc conversion precision 12-bit/10 adjustable
Date : 2025-11-20 Size : 477kb User : zhangyujun
dual_RAM Downloaded：0: actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog HDL
Date : 2025-11-20 Size : 594kb User : zhangyujun
RTC Downloaded：0: actel fpga development board fusion startkit test routines, including the complete works of several verilog HDL source file
Date : 2025-11-20 Size : 2.13mb User : zhangyujun
fast-crc_latest.tar Downloaded：0: 5x4Gbps CRC generator designed with standard cells
Date : 2025-11-20 Size : 4.55mb User : aliakbar
SPI Downloaded：0: STC5A60S2 microcontroller SPI communication, the source program needs to contact me
Date : 2025-11-20 Size : 115kb User : jiajia
287eb141911b Downloaded：0: Prepared using VHDL usb controller, usb reading and writing to achieve control and chip select.
Date : 2025-11-20 Size : 4kb User : 曾强

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