actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog HDL

dual_RAM\Project\DualPortRAM\designer\impl1\designer.log
........\.......\...........\........\.....\designer_genhdl.log
........\.......\...........\........\.....\top.adb
........\.......\...........\........\.....\....dtf\verify.log
........\.......\...........\........\.....\top.ide_des
........\.......\...........\........\.....\top.pdb
........\.......\...........\........\.....\top.pdb.depends
........\.......\...........\........\.....\top.stp
........\.......\...........\........\.....\top.tcl
........\.......\...........\........\.....\..._fp\$$FlashPro_FPBBALTLPT1.L$$
........\.......\...........\........\.....\......\projectData\top.pdb
........\.......\...........\........\.....\......\top.log
........\.......\...........\........\.....\......\top.pro
........\.......\...........\DualPortRAM.prj
........\.......\...........\hdl\hdlsynchk.tcl
........\.......\...........\...\rec.v
........\.......\...........\...\send.v
........\.......\...........\...\top.v
........\.......\...........\...\writeram.v
........\.......\...........\simulation\meminit.dat
........\.......\...........\..........\modelsim.ini
........\.......\...........\..........\modelsim.ini.sav
........\.......\...........\..........\RAM2k8_R0C0.mem
........\.......\...........\..........\RAM2k8_R0C1.mem
........\.......\...........\..........\RAM2k8_R0C2.mem
........\.......\...........\..........\RAM2k8_R0C3.mem
........\.......\...........\.martgen\RAM2k8\RAM2k8.cxf
........\.......\...........\........\......\RAM2k8.gen
........\.......\...........\........\......\RAM2k8.log
........\.......\...........\........\......\RAM2k8.shx
........\.......\...........\........\......\RAM2k8.v
........\.......\...........\........\......\RAM2k8_R0C0.mem
........\.......\...........\........\......\RAM2k8_R0C1.mem
........\.......\...........\........\......\RAM2k8_R0C2.mem
........\.......\...........\........\......\RAM2k8_R0C3.mem
........\.......\...........\........\RAM2k8_work.ixf
........\.......\...........\........\smartgen.aws
........\.......\...........\.ynthesis\.recordref
........\.......\...........\.........\stdout.log
........\.......\...........\.........\.yntmp\sap.log
........\.......\...........\.........\......\top.msg
........\.......\...........\.........\......\top.plg
........\.......\...........\.........\......\top_flink.htm
........\.......\...........\.........\......\top_srr.htm
........\.......\...........\.........\......\top_toc.htm
........\.......\...........\.........\top.areasrr
........\.......\...........\.........\top.edn
........\.......\...........\.........\top.fse
........\.......\...........\.........\top.htm
........\.......\...........\.........\top.map
........\.......\...........\.........\top.sap
........\.......\...........\.........\top.sdf
........\.......\...........\.........\top.srd
........\.......\...........\.........\top.srm
........\.......\...........\.........\top.srr
........\.......\...........\.........\top.srs
........\.......\...........\.........\top.tlg
........\.......\...........\.........\top_drc.rpt
........\.......\...........\.........\top_sdc.sdc
........\.......\...........\.........\top_syn.prj
........\.......\...........\.........\traplog.tlg
........\.......\...........\viewdraw\vf\project.lst
........\.......\...........\........\viewdraw.ini
........\Source File\rec.v
........\...........\send.v
........\...........\top.v
........\...........\waveperl.log
........\...........\writeram.v
........\Project\DualPortRAM\designer\impl1\top_fp\projectData
........\.......\...........\........\.....\simulation
........\.......\...........\........\.....\top.dtf
........\.......\...........\........\.....\top_fp
........\.......\...........\........\impl1
........\.......\...........\smartgen\RAM2k8
........\.......\...........\.ynthesis\syntmp
........\.......\...........\viewdraw\sch
........\.......\...........\........\sym
........\.......\...........\........\vf
........\.......\...........\........\wir
........\.......\...........\component
........\.......\...........\c

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