VHDL-FPGA-Verilog List Page 2830

VHDL-FPGA-Verilog list

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EDA1 Downloaded：0: Completion of a binary full subtracter design, implementation, respectively, using the text input method, hierarchical design, are based on half adder and logic gates.
Date : 2025-11-20 Size : 382kb User : 周旋
EDA2 Downloaded：0: Die Variable Counter Design: Setting a control bit M, requires M = 0, module 23 counts M = 1, module 109 counts count the results of dynamic digital control said.
Date : 2025-11-20 Size : 157kb User : 周旋
EDA3add Downloaded：0: Sequence signal generator and detector design: The Design and Implementation of a serial sequence of state machine design of the detector, the first design (schematic diagram input) sequence signal generator sequence: 01
Date : 2025-11-20 Size : 176kb User : 周旋
EDA4 Downloaded：0: Digital clock design: dynamic digital display, hour can be preset to 12-hour time display and 24-hour time display a regulatory key target for regulating the number of digits. Regulating the contents of the sensitive, su
Date : 2025-11-20 Size : 204kb User : 周旋
EDA5 Downloaded：0: Traffic light controller design: 1. With MR (the main red), MY (Master Wong), MG (Master Green), CR (township red), CY (Rural yellow), CG (village green) six traffic lights need to control 2. → red traffic light from gre
Date : 2025-11-20 Size : 1013kb User : 周旋
EDA6 Downloaded：0: Music Generator implementation. Select the music " Butterfly Lovers" in the butterfly section.
Date : 2025-11-20 Size : 736kb User : 周旋
LabDesign Downloaded：0: A Nice Lab Design Contains Different Implementations to different logic functionalistsand simulation to PIC16F84A using Verilog
Date : 2025-11-20 Size : 1.06mb User : ayd
spdmeasure Downloaded：0: Pulse velocity, with the VERILOG language, automatically skip files
Date : 2025-11-20 Size : 22.84mb User : dingweisen
USB_LOOP Downloaded：0: Verilog program is based on the USB chip 68013, FPGA50T, realized between two computers using two 68013 and one FPGA50T to communicate
Date : 2025-11-20 Size : 2kb User : zero
cpilegame Downloaded：0: cpilegame - cpilegame by varilog
Date : 2025-11-20 Size : 323kb User : dongguk
Frame_2D Downloaded：0: A 2D frame building of ANSYS developed by myself, can calculate modal, static and dynamic response
Date : 2025-11-20 Size : 5kb User : Wang Yan
Fredevider_n Downloaded：0: Any even multiple of the frequency divider N VHDL language, compiler MAX_PLUS2
Date : 2025-11-20 Size : 24kb User : 黑雾

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