VHDL-FPGA-Verilog List Page 2825

VHDL-FPGA-Verilog list

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MYPROJECT Downloaded：0: CP2200 & FPGA
Date : 2025-11-20 Size : 245kb User : 张明
Storm Downloaded：0: Storm can be BLASTFASTAPfamProtParam of protein sequence analysis software and the results output to the database. Zip
Date : 2025-11-20 Size : 23.63mb User : 陈虎
sim_uart Downloaded：0: verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC,
Date : 2025-11-20 Size : 2kb User : 周西东
dct Downloaded：0: all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is
Date : 2025-11-20 Size : 1kb User : haziq36
cf_interleaver_6_16 Downloaded：0: 6*16interleaver
Date : 2025-11-20 Size : 2kb User : 小黑豆
sdram Downloaded：0: Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 001
Date : 2025-11-20 Size : 14kb User : 周西东
lift Downloaded：1: The project to design an elevator control system, the traditional elevator control system is only required to achieve an elevator control, and to design an implementation of this title two elevator linkage of the elevato
Date : 2025-11-20 Size : 1.32mb User : chdj
fpga Downloaded：0: Based on field programmable gate array (Fie ld Programmab le Ga teA rrays, FPGA) hardware platform and the background difference algorithm to design a static background Video moving target detection and tracking system,
Date : 2025-11-20 Size : 556kb User : chdj
ARM_register Downloaded：0: 将中文译成英语 ARM register set design source code, the use of Verilog programming, you can compile the simulation pass.
Date : 2025-11-20 Size : 2kb User : jwj
Teletext_Core_Files_890607 Downloaded：0: A teletext extraction source code for WST PAL B standard
Date : 2025-11-20 Size : 14kb User : Ali
mem32_to_pcitarget_verilog Downloaded：0: This design example shows how to implement interface between 32-bit pci target Altera megafunction instantiation and a 32-bit synchronous memory
Date : 2025-11-20 Size : 20kb User : minitman
mem64_to_pcitarget_verilog Downloaded：0: This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunction and 64-bit synchronous memory
Date : 2025-11-20 Size : 26kb User : minitman

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