VHDL-FPGA-Verilog List Page 283

VHDL-FPGA-Verilog list

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18.UART Downloaded：0: The use of verilog language FPGA on the serial program to achieve, can achieve 9600 baud rate transceiver function, and occupy less logical unit
Date : 2025-05-30 Size : 503kb User : 张仑仑
spi_master Downloaded：0: Using verilog language to achieve the SPI under the host mode, the baud rate is one-fifth of the crystal clock, send stable
Date : 2025-05-30 Size : 109kb User : 张仑仑
ROM Downloaded：0: Use verilog language to achieve altera under the cycloneII series FPGA on-chip ROM to create, read and write, call IP core
Date : 2025-05-30 Size : 36kb User : 张仑仑
ALTERA_FPGA_SDRAM Downloaded：0: Use ALTERA s FPGA to control SDRAM s verilog program
Date : 2025-05-30 Size : 12.45mb User : 李
21_flash_ddr_lcd Downloaded：0: flash and ddr3 verilogHDL soft
Date : 2025-05-30 Size : 6.82mb User : 冰海情
11_ddr3_test Downloaded：0: ddr3 veirloghdl operater xinlinx FPGA
Date : 2025-05-30 Size : 5.75mb User : 冰海情
fm Downloaded：0: FM altera fpga veriloghdl
Date : 2025-05-30 Size : 1.18mb User : 冰海情
SPI Downloaded：0: Verilog is used to display the flow lamp via the SPI protocol.
Date : 2025-05-30 Size : 210kb User : lizheqing
tinycpufiles Downloaded：0: The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is a Quartus project, and it can run well on Altera MAXII CPLD, and it is conveniently change to other FPGAs. The CPU used 200
Date : 2025-05-30 Size : 59kb User : 肖海云
CLOCK Downloaded：0: Implement electronic clock, use CYCLONE V, has been successfully verified, attach the project file
Date : 2025-05-30 Size : 14.98mb User : 陈俊奕
LSD Downloaded：0: VHDL language used to write the water lights for the latest CYCLONE V test environment, engineering documents attached, pin assignment has been completed. Experiments need to book contact 2942551049@qq.com
Date : 2025-05-30 Size : 6.22mb User : 陈俊奕
FPGA_exp2 Downloaded：0: Adjust digital display files for CYCLONE II development board, using VHDL language, it is very suitable for transplantation into digital clock to realize the function of regulation time. Simple multi-module design.
Date : 2025-05-30 Size : 6.49mb User : 陈俊奕

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