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VHDL-FPGA-Verilog list
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1. Source file in src directory, QII Proj project files in the directory 2. Program implementation function is displayed on the VGA display colored stripes, a total of 8 colors, you can use the embedded logic analyzer ob
Date : 2025-11-21 Size : 227kb User : 陈亮

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1, ps/2 keyboard input, through the led display ascii code 2, wait for 1s in the input character lcd display 3, in which key on the keyboard is used to clear the screen backspce 4, when the lcd display full of character,
Date : 2025-11-21 Size : 838kb User : 陈亮

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Rom storage using VHDL language, you can choose a different storage space, there are several control signals
Date : 2025-11-21 Size : 55kb User : Grace

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psk信号发生器
Date : 2025-11-21 Size : 364kb User : aaa111

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: The digital frequency meter based on XILINX development terrace generates 100 KHz square waves by a supply oscillator within FPGA. The nixietubes of the board, which is available of 6 significant figures, are used to d
Date : 2025-11-21 Size : 121kb User : wen

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FAQ about the using of DDS
Date : 2025-11-21 Size : 616kb User : shark

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The archive contains the i2c core design specifications required for the detailed timing and preparation of the core with the verilog source code, the simulation module.
Date : 2025-11-21 Size : 4.21mb User : jinyongchen

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Oscilloscope VHDL, in Traditional Chinese, may need support to look at the content, we want to help.
Date : 2025-11-21 Size : 223kb User : bolinjian

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The output(out1) is the product of input(neg and pos)
Date : 2025-11-21 Size : 14kb User : jimmy

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vhdl code for full adder program using libero software.
Date : 2025-11-21 Size : 1kb User : swap

This is a 3 input majority detector.It have 3 input(a,b,c) and 1 output(y)
Date : 2025-11-21 Size : 17kb User : jimmy

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User Guide
Date : 2025-11-21 Size : 765kb User : portia
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