VHDL-FPGA-Verilog List Page 2692

VHDL-FPGA-Verilog list

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qiche.doc Downloaded：0: With the rapid economic and social development of more and more people have their own car, safe driving more and more attention has been paid, and taillights flash the correct play on the safe driving of the role can not
Date : 2025-11-21 Size : 298kb User : quanguoxiang
A20 Downloaded：0: A20 地址线问题.doc
Date : 2025-11-21 Size : 5kb User : 刘禄
RS_coder Downloaded：0: Based on the RS encoder verilog absolute utility
Date : 2025-11-21 Size : 174kb User : 吴
ff_mul Downloaded：0: Rs encoder based on Galois field multiplier verilog
Date : 2025-11-21 Size : 1kb User : 吴
ps2 Downloaded：0: This procedure is based on FPGA implementation of the ps/2 keyboard interface circuit, able to display the digital keyboard input!
Date : 2025-11-21 Size : 1.93mb User : 张东林
freq Downloaded：0: This procedure is based on the vhdl language 8 16 hex frequency, frequency range tested 1HZ ~ 100MHZ.
Date : 2025-11-21 Size : 679kb User : 张东林
dds Downloaded：0: verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
Date : 2025-11-21 Size : 2.47mb User : linzi
div_any_nodd Downloaded：0: Verilog language using any odd hardware divide, and the modelsim simulation testing using ise11.1
Date : 2025-11-21 Size : 498kb User : linzi
div_n_0_5 Downloaded：0: Using an arbitrary odd number n+0.5 verilog divide, the use of simulation testing ise11.1 and modelsim se6.5
Date : 2025-11-21 Size : 770kb User : linzi
ffj Downloaded：0: Tap hardware language, the use of simulation testing QUARTUS2
Date : 2025-11-21 Size : 2.19mb User : linzi
stopwatch1 Downloaded：0: stopwatch : verilog source code
Date : 2025-11-21 Size : 1.07mb User : hanjaeyoung
watch(2) Downloaded：0: digital watch : verilog source code
Date : 2025-11-21 Size : 390kb User : hanjaeyoung

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