VHDL-FPGA-Verilog List Page 2590

VHDL-FPGA-Verilog list

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behavioral_counter Downloaded：0: -- This example implements a behavioral counter with load, clear, and up/down features. -- It has not been optimized for a particular device architecture, so performance may vary. Altera recommends using the lpm_counter
Date : 2025-11-22 Size : 1kb User : vasil
8051 Downloaded：0: 51 SCM FPGA soft core model, SCM 51, the smallest available trim system, external expansion
Date : 2025-11-22 Size : 2.02mb User : 袁方
S9_PS2_LCD Downloaded：0: 1, ps/2 keyboard input, through the led display ascii code 2, wait for 1s in the input character lcd display 3, in which key on the keyboard is used to clear the screen backspce 4, when the lcd display full of character,
Date : 2025-11-22 Size : 9kb User : 袁方
S2_38yima Downloaded：0: 1 copy of the program 3/8 decoder function 2, 3 DIP switch from the input, led output.
Date : 2025-11-22 Size : 58kb User : 袁方
S8_VGA Downloaded：0: 1. Source file in src directory, QII Proj project files in the directory 2. Program implementation function is displayed on the VGA display colored stripes, a total of 8 colors, you can use the embedded logic analyzer ob
Date : 2025-11-22 Size : 225kb User : 袁方
S5_BOARD_ID Downloaded：0: 1, the program is the 7-segment display of the scan output scans example 2, using the scanning principle four digital display four different figures, but the data input is a set of bus
Date : 2025-11-22 Size : 63kb User : 袁方
PIANo Downloaded：0: (1) Download " KX232_PIANO_C5T" folder in the sof file. (2) connected to the serial communication lines, and the PC machine communication. (3) " FOR_PC_FILE" folder, double-click to open the PC software &
Date : 2025-11-22 Size : 48kb User : 袁方
B08040825_2_8 Downloaded：0: Curriculum design report, do the 28 decoder, it is useful for reference
Date : 2025-11-22 Size : 425kb User : sdfsdfsdf
8BIT-VHD Downloaded：0: 8 phase and other comparators. . . Very practical, curriculum design purposes. . . Very suitable for students. . .
Date : 2025-11-22 Size : 2.93mb User : sdfsdfsdf
v7 Downloaded：0: Here is a Fifo impementation in vhdl with a 8 bit input and 8 bit output, reset and a synchronisation for reading and writing with different clocks
Date : 2025-11-22 Size : 11kb User : alghost
DXPintegrated-library Downloaded：0: dxp integrated library DXP this guide to know how to use, create and modify an integrated library. Schematic diagram of an integrated library will be associated with their PCB assembly and (or) SPICE models or signal int
Date : 2025-11-22 Size : 1.36mb User : shl
VerilogCodingGuidelines Downloaded：0: verilog coding guide lines
Date : 2025-11-22 Size : 180kb User : rbacha88

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