VHDL-FPGA-Verilog List Page 2475

VHDL-FPGA-Verilog list

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LCD1602 Downloaded：0: 1602 display driver, I have tested successfully in my own test board, you need slightly modified according to your own test board
Date : 2025-11-23 Size : 452kb User : 王建伟
xiayuwen Downloaded：0: This program is the Xia Yu Wen digital system design tutorial E2PROM complete file, including the signal generation module, E2PROM reader module, E2PROM simulation module, and run successfully on the ISE, the test correc
Date : 2025-11-23 Size : 49kb User : 王建伟
256.16-RAM Downloaded：0: VHDL language, achieving 256 ×16RAM block .A little change can change the capacity of the block RAM
Date : 2025-11-23 Size : 260kb User : 王建伟
Telephone-billing-programme Downloaded：0: Telephone billing function program, VHDL language, has been measured, without any problems
Date : 2025-11-23 Size : 16kb User : 王建伟
16-bit-high-speed-digital-correlator Downloaded：0: 16-bit high-speed digital correlator modules, VHDL language
Date : 2025-11-23 Size : 3kb User : 王建伟
FPGA---Serial Downloaded：0: FPGA implementation of the serial program, including top-level calling code.
Date : 2025-11-23 Size : 4kb User : 周华飞
state-machine-design Downloaded：0: State machine design a good example of hard work, VHDL language.Ｉthink it will help verilog　learners
Date : 2025-11-23 Size : 185kb User : 王建伟
ROM Downloaded：0: The ROM circuit with a combination of functional modules, VHDL language
Date : 2025-11-23 Size : 174kb User : 王建伟
frame Downloaded：0: Long frame sync clock generation function modules, VHDL language
Date : 2025-11-23 Size : 183kb User : 王建伟
reg Downloaded：0: Synchronous register (Behavioral representation) - an 8-bit register to store the values of switches SW7-SW0 on the outputs LEDR7-LEDR0 as the key KEY0 is pressed.
Date : 2025-11-23 Size : 237kb User : dawnofangry
shiftreg Downloaded：0: Shift regisiter altera de1 board example
Date : 2025-11-23 Size : 1kb User : Jhon
usb20arm_by Downloaded：0: vhdl for usb2.0
Date : 2025-11-23 Size : 3kb User : gerile

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