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VHDL-FPGA-Verilog list
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VHDL language implementation with a counter N divider divider
Date : 2025-11-23 Size : 3kb User : xiaojing

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the design introduced a method to use DPLL,we can get the local clock from the signal
Date : 2025-11-23 Size : 909kb User : 123456

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The file describe the RS code and decode, there are a lot of examples in it, so you can understand it easily
Date : 2025-11-23 Size : 1015kb User : 123456

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Serial VHDL program, Xilinxṩ test was successful.
Date : 2025-11-23 Size : 11kb User : weixin

Graphics accelerator
Date : 2025-11-23 Size : 2.59mb User : Manoj

FFT of the VHDL language for the source code is more comprehensive features, but my teacher said is also relatively more complicated
Date : 2025-11-23 Size : 63kb User : wangliang

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LCD timer small alarm clock, clock chips by 51 and 1302
Date : 2025-11-23 Size : 125kb User : hxh

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Can control two crossroads red, yellow and green lights. Let it according to the specific rule changes. Use of Quartus Ⅱ simulation design results
Date : 2025-11-23 Size : 566kb User : Nana Wang

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I2C master eeprom
Date : 2025-11-23 Size : 2.19mb User : 王敏

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The simplest routines Nios is no need to change, download the application directly to the target board
Date : 2025-11-23 Size : 34.01mb User : wuchunfa

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The des;gn of PCI04 bus multi-function extended card based on CPLD technology
Date : 2025-11-23 Size : 70kb User : 董柏林

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VHDL language in the code switch control method of tube m word
Date : 2025-11-23 Size : 9kb User : 周明炜
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