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VHDL-FPGA-Verilog list
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about and gate user with verilog hdl
Date : 2025-11-23 Size : 223kb User : 王强

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how to get the function of reset with verilog hdl
Date : 2025-11-23 Size : 371kb User : 王强

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create the fre with verilog hdl
Date : 2025-11-23 Size : 542kb User : 王强

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The programs of serial port based on ISE10.1.
Date : 2025-11-23 Size : 842kb User : 张根华

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ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
Date : 2025-11-23 Size : 3kb User : 钟雪美

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By the development board four keyboards, and then show the different digital data on
Date : 2025-11-23 Size : 92kb User : zhangbaohong

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The default is the digital dynamic display 01234567, but can modify the data humane!
Date : 2025-11-23 Size : 135kb User : zhangbaohong

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failed to translate
Date : 2025-11-23 Size : 86kb User : 朱恩培

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failed to translate
Date : 2025-11-23 Size : 138kb User : 朱恩培

This module is designed to implement parallel to serial conversion
Date : 2025-11-23 Size : 1kb User : 郭丽龙

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step count set
Date : 2025-11-23 Size : 752kb User : zlzueuec

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This course is designed based on a computer, the state machine is designed cpld technology of the taillights controller.
Date : 2025-11-23 Size : 6kb User : 孙浩
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