VHDL-FPGA-Verilog List Page 2270

VHDL-FPGA-Verilog list

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AND2V1 Downloaded：0: about and gate user with verilog hdl
Date : 2025-11-23 Size : 223kb User : 王强
reset Downloaded：0: how to get the function of reset with verilog hdl
Date : 2025-11-23 Size : 371kb User : 王强
create_pulse Downloaded：0: create the fre with verilog hdl
Date : 2025-11-23 Size : 542kb User : 王强
uart-232 Downloaded：0: The programs of serial port based on ISE10.1.
Date : 2025-11-23 Size : 842kb User : 张根华
adc Downloaded：0: ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
Date : 2025-11-23 Size : 3kb User : 钟雪美
DECL7S Downloaded：0: By the development board four keyboards, and then show the different digital data on
Date : 2025-11-23 Size : 92kb User : zhangbaohong
seg70 Downloaded：0: The default is the digital dynamic display 01234567, but can modify the data humane!
Date : 2025-11-23 Size : 135kb User : zhangbaohong
sin Downloaded：0: failed to translate
Date : 2025-11-23 Size : 86kb User : 朱恩培
fsm_exp Downloaded：0: failed to translate
Date : 2025-11-23 Size : 138kb User : 朱恩培
parallel-to-serial-conversion Downloaded：0: This module is designed to implement parallel to serial conversion
Date : 2025-11-23 Size : 1kb User : 郭丽龙
jibu Downloaded：0: step count set
Date : 2025-11-23 Size : 752kb User : zlzueuec
CPLDCARLIGHTSCONTROL Downloaded：0: This course is designed based on a computer, the state machine is designed cpld technology of the taillights controller.
Date : 2025-11-23 Size : 6kb User : 孙浩

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