VHDL-FPGA-Verilog List Page 2239

VHDL-FPGA-Verilog list

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mux_4_1 Downloaded：0: In the Quartus II VHDL language using the four selection procedures for a data selector
Date : 2025-11-24 Size : 172kb User : 林燕
Priority-encoder Downloaded：0: In the Quartus II VHDL language using the priority encoder program
Date : 2025-11-24 Size : 179kb User : 林燕
full_adder-and-half_adder Downloaded：0: In the Quartus II VHDL language using the full adder and half adder program, full-adder is called a half adder to achieve.
Date : 2025-11-24 Size : 180kb User : 林燕
nand2_1 Downloaded：0: In Quartus II using VHDL language with the operator to achieve, " and not" gate proce
Date : 2025-11-24 Size : 146kb User : 林燕
nand_2 Downloaded：0: In Quartus II using VHDL language with the truth table to achieve the non-gate process.
Date : 2025-11-24 Size : 158kb User : 林燕
LCD2 Downloaded：0: LCD program written in VHDL, it can show our company website.
Date : 2025-11-24 Size : 559kb User : 夏晓
decoder_latest Downloaded：0: mp3 decoder in vhdl from opencores
Date : 2025-11-24 Size : 34kb User : echip
SEED-DEC28335v-1.4 Downloaded：0: SEED-DEC28335v1. 4 Chinese instruction
Date : 2025-11-24 Size : 433kb User : shenji
SEED-XDS560PLUS Downloaded：0: SEED-XDS560PLUS simulators installation, use guide
Date : 2025-11-24 Size : 1.13mb User : shenji
EDA_dianzhen Downloaded：0: Verilog language written using the 16* 16 dot matrix, to achieve left, right, pause, reset and other functions, you can customize RAM, change the display content.
Date : 2025-11-24 Size : 773kb User : 李建
xulie Downloaded：0: Using the state machine to write the serial checker to 1110 1, for example, is to specify the state machine of the type of writing and writing rules
Date : 2025-11-24 Size : 53kb User : 李建
EDAkeshe--huanhuan Downloaded：0: This file contains the EDA curriculum design waveform generator is designed to achieve waveform of the signal' s amplitude and frequency are adjustable
Date : 2025-11-24 Size : 364kb User : huanhuan

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