VHDL-FPGA-Verilog List Page 2222

VHDL-FPGA-Verilog list

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VHDL100 Downloaded：0: Examples of VHDL project 100, the content is better for beginners, school speech teacher, easy to understand! To share with you
Date : 2025-11-24 Size : 215kb User : hello
Verilog-HDL Downloaded：0: verilog HDL of materials, including its language specification and the like, suitable for beginners
Date : 2025-11-24 Size : 4.62mb User : hello
add Downloaded：0: SCANNER CORE MODULE FOR VERILOG USERS
Date : 2025-11-24 Size : 9kb User : Ritesh Deshmukh
qiangdaqi Downloaded：0: Responder, through the FPGA to achieve a variety of functions, curriculum design done, because the code is simple, there is no sub-module, a program finished.
Date : 2025-11-24 Size : 391kb User : liuye
shuzizhong Downloaded：0: Responder, through the FPGA to achieve a variety of functions, curriculum design done, because the code is simple, there is no sub-module, a program finished.
Date : 2025-11-24 Size : 582kb User : liuye
quartus_error Downloaded：0: On the Verilog HDL language integrated development environment quartus some of the common error analysis
Date : 2025-11-24 Size : 12kb User : qk
VGAcharactor Downloaded：0: CPLD driver in analog VGA signal, and read and write on the Sram
Date : 2025-11-24 Size : 1.36mb User :
27-examles-of-VHDL Downloaded：0: This package contains a number of very practical examples and a detailed description of the preparation of ideas, for your reference.
Date : 2025-11-24 Size : 1.22mb User : 杨安娜
DDS_verilog Downloaded：0: Verilog achieved using the DDS generator, source code has been compiled by board-level simulation debugging, modularity can be directly used.
Date : 2025-11-24 Size : 2kb User : 杨安娜
jianpanqudou Downloaded：0: Mainly VHDL language keyboard to shake procedure, it is correct, it is practical
Date : 2025-11-24 Size : 99kb User : 王聪
Clk50M_div_1HZ Downloaded：0: Clk50M_div_1HZ, using counter this study, frequency counter, onboard 50MHz clock frequency of 1Hz, frequency results in the form of LED lights display. Download the circuit to the FPGA, you will find LED0 will be the fre
Date : 2025-11-24 Size : 317kb User : 王晨
Encoder4_2 Downloaded：0: Encoder4_2, with a priority encoder to complete this experiment, but the 4-2 priority encoder to toggle switch SW [3 .. 0] as the input source (input switch is high on the dial), which SW [3 ] takes precedence over the S
Date : 2025-11-24 Size : 209kb User : 王晨

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