VHDL-FPGA-Verilog List Page 2183

VHDL-FPGA-Verilog list

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60jiafajishuqi Downloaded：0: vhdl language addition of 60 binary counter can be used directly
Date : 2025-11-24 Size : 240kb User : 王涛
da1_test Downloaded：0: ad conversion, using the Altera Cyclone FPGA (EP1C6-PQ240) chip, in QuartusII 9.0 compiler, a better reference value, has been tested.
Date : 2025-11-24 Size : 193kb User : gxu
ad1_da1_test Downloaded：0: The first road to the first AD conversion result is output Road DA, compiled in QuartusII 9.0, there is a good reference value, has been tested.
Date : 2025-11-24 Size : 255kb User : gxu
cpld Downloaded：0: cpld entry basis only for beginners looking to guide their children' s shoes Oh you
Date : 2025-11-24 Size : 6kb User : 郭坤平
QUARTUS-II Downloaded：0: Quartus ii entry basis only for beginners looking to guide their children' s shoes Oh you
Date : 2025-11-24 Size : 1.97mb User : 郭坤平
vhdlPprimerPbhaskar.pdf Downloaded：0: VHDL file Author by bhaskar
Date : 2025-11-24 Size : 1.15mb User : bhaskar
digital-oscillograph Downloaded：0: verilog language, digital oscilloscope, sampling, frequency measurement, the measured rate, display!
Date : 2025-11-24 Size : 821kb User : bixiangru
8.14-MPSK-VHDL Downloaded：0: MASK modulation and simulation of a VHDL program verified through debugging
Date : 2025-11-24 Size : 78kb User : liufei
ms430jianpansaomiao33jianpan Downloaded：0: 4* 4 keyboard scan program 1602 LCD ms430
Date : 2025-11-24 Size : 9kb User : 安坤
Precision-frequency-meter--etc. Downloaded：0: Precision frequency meter, etc.
Date : 2025-11-24 Size : 980kb User : zz
WASH Downloaded：0: Washing machine simulation program written in VHDL, can forward 20s, pause 10s, reverse 20s, pause 10s, may set the initial time to run!
Date : 2025-11-24 Size : 377kb User : liuyong
syb Downloaded：0: Voltmeter display, can be measured within the range 0 ~ 5V voltage size! Using digital display value!
Date : 2025-11-24 Size : 295kb User : liuyong

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