VHDL-FPGA-Verilog List Page 2129

VHDL-FPGA-Verilog list

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Servo-using-the-program Downloaded：0: This article is written in the language with AVR atmega8 example of a servo control, PWM signal with a single-chip pulse control steering angle jitter.
Date : 2025-11-24 Size : 25kb User : panmingfu
top Downloaded：0: Can achieve multiple choice, using verilog, clear and easy to understand code
Date : 2025-11-24 Size : 1kb User : hehaihai
PWM Downloaded：0: Freescale MCU PWM pulse code modulation output, used in small motor control, intelligent car
Date : 2025-11-24 Size : 1kb User : 刘海波
DAC0832 Downloaded：0: MCU with digital to analog converter DAC0832 and the produce was sawtooth function. This program has been through debugging, really feasible.
Date : 2025-11-24 Size : 8kb User : xu
A402-OutputTFT-LCDDriverICWithPower Downloaded：0: 402 output thinfilm transistorliqu idcrystal display(TFT-LCDdriver integrated circui(ICwith power controlbasedon the number of color stobe displaye disdescribed. Toachievethistypeofpowercontrol,referencevoltagebuffersare
Date : 2025-11-24 Size : 518kb User : xuzhitong05
msp430_FPGAcommunicatecode Downloaded：0: This code is msp430f149 fpga implementation of both communication and procedures, contains its own set of protocols
Date : 2025-11-24 Size : 30kb User : 周抗力
fft Downloaded：0: FFT-based FPAG
Date : 2025-11-24 Size : 10.35mb User : answer
maopao Downloaded：0: Implementation of bubble sort using verilog. Can be used for any number of rows of data in order.
Date : 2025-11-24 Size : 197kb User : sue
FIFO Downloaded：0: This file contains the simulation files and project files, complete function is to achieve FIFO.
Date : 2025-11-24 Size : 4kb User : sue
ram Downloaded：0: Using verilog implementation of dual-port RAM. File contains the project files, simulation files, easy to use.
Date : 2025-11-24 Size : 214kb User : sue
jdclk Downloaded：0: Using verilog implementation step delay circuit, is the core of the digital oscilloscope.
Date : 2025-11-24 Size : 276kb User : sue
max118FPGA Downloaded：0: The use of written control max118 verilog program. File contains the simulation waveform files.
Date : 2025-11-24 Size : 280kb User : sue

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