VHDL-FPGA-Verilog List Page 1977

VHDL-FPGA-Verilog list

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buzzerverilog Downloaded：0: Use of language buzzer to sing, there are detailed code and comments
Date : 2025-09-19 Size : 402kb User : 邹耀飞
DE2-platform-hardware-audio-playback Downloaded：0: Purely on the DE2 platform hardware audio playback experiment
Date : 2025-09-19 Size : 1.1mb User : rjy
triangular_wave Downloaded：0: sr flipflop verilog you can simulate it in any eda tool
Date : 2025-09-19 Size : 1kb User : zakirhussain
Stepper_control Downloaded：0: verilog code for steeper motor control use eda for testing it
Date : 2025-09-19 Size : 1kb User : zakirhussain
f340_pov_led_ Downloaded：0: Using thirteen LEDs display rotation, display clock, there are Chinese characters
Date : 2025-09-19 Size : 47kb User : 张静泉
ad7864 Downloaded：0: ad7864 control program
Date : 2025-09-19 Size : 1kb User : pioneer
EDA-shuzizhong Downloaded：0: Using EDA software to realize the digital clock design, with detailed code
Date : 2025-09-19 Size : 1.02mb User : 张静泉
zuhedianlu Downloaded：0: Combinational circuit design, to provide some reference, so that they can better understand
Date : 2025-09-19 Size : 182kb User : 张静泉
shixudianlu Downloaded：0: The timing circuit design, to provide some reference, so that they can better understand
Date : 2025-09-19 Size : 4.49mb User : 张静泉
traffic-light Downloaded：0: Verilog HDL code to control bi-direction traffic light
Date : 2025-09-19 Size : 1kb User : 吴原远
uart-VHDL Downloaded：0: uart-VHDL add parity check bit rate is 1152
Date : 2025-09-19 Size : 5kb User :
modelsim Downloaded：0: modelsim is a very important development in the FPGA timing simulation aids, which contains details of modelsim use of this software is used for instructions. Make you a very simple to learn!
Date : 2025-09-19 Size : 1.83mb User : sailonghuang

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