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VHDL-FPGA-Verilog list
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Jtag-uart IP core in SOPC
Date : 2025-09-19 Size : 5kb User : zy

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EPCS IP core in SOPC
Date : 2025-09-19 Size : 4kb User : zy

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timer ip core in SOPC
Date : 2025-09-19 Size : 2kb User : zy

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pll ip core in SOPC
Date : 2025-09-19 Size : 3kb User : zy

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Altera NIOS II uart DRIVER
Date : 2025-09-19 Size : 7kb User : zy

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Verilog implementation of a stopwatch program
Date : 2025-09-19 Size : 94kb User :

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Q24DTU hardware design, hardware design for the Q24 fu
Date : 2025-09-19 Size : 130kb User : 刘小瑜

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Avalon bus-based controller design of TFT LCD
Date : 2025-09-19 Size : 140kb User : 刘小瑜

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CABAC to achieve this is to introduce the information of the FPGA implementation
Date : 2025-09-19 Size : 2.53mb User : 钟普

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This achieved JPEG2000MQ encoding the file, you need to download
Date : 2025-09-19 Size : 580kb User : 钟普

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In NiosII system successfully transplanted the uc/GUI3.98.The used hardwares conclude DE2 development board and TRDB-LTM.It s display resolution is 400* 240,and the color model is 332, it also can be touched.
Date : 2025-09-19 Size : 14.32mb User : feng

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EDA test sequence signal detector and variable-counter model, project files and VHDL files
Date : 2025-09-19 Size : 893kb User : 邓泽林
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