VHDL-FPGA-Verilog List Page 1934

VHDL-FPGA-Verilog list

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FIR_cautruc_truc_tiep Downloaded：0: this is FIR filter by VHDL
Date : 2025-09-18 Size : 1kb User : thuyhang
Asynfifo Downloaded：0: Write asynchronous fifo
Date : 2025-09-18 Size : 117kb User : 陈冬
qudou Downloaded：0: To achieve a de-jitter function keys, board debug, relatively easy to
Date : 2025-09-18 Size : 256kb User : 飞天
LCD1602-display Downloaded：0: verilog programming shown on the lcd1602 character, learning board verification
Date : 2025-09-18 Size : 773kb User : 飞天
adda Downloaded：0: This an adda verilog data collection procedures, components is complete
Date : 2025-09-18 Size : 1.09mb User : zhangQiping
led-streaming Downloaded：0: verilog implementation led light water, the board verify the correctne
Date : 2025-09-18 Size : 342kb User : 飞天
music Downloaded：0: Verilog implementation buzzer with music, the board verify the correct
Date : 2025-09-18 Size : 620kb User : 飞天
vga_display Downloaded：0: verilog achieve vga display, verify the correctness of the board
Date : 2025-09-18 Size : 2.34mb User : 飞天
VHDL Downloaded：0: VHDL design of experiments, including four reversible counters, four reversible binary code- Gray code converter design, the sequence detector design, the ROM-based sine wave generator design, digital lock design and imp
Date : 2025-09-18 Size : 48kb User : 张联合
sram_duxie Downloaded：0: Control with FPGA SRAM read and write procedures
Date : 2025-09-18 Size : 1kb User : xiao
jiaotongdeng Downloaded：0: Traffic lights, functions: L0.0 main road red L0.1 main road yellow L0.2 main road green L1.0 slip red L1.1 slip yellow L1.2 green branch
Date : 2025-09-18 Size : 9kb User : 雷莲波
1602P24C08P4X4mimashuo Downloaded：0: Single-chip 4x4 lock:** 0** 1** 2** 3**** 4** 5** 6** 7** 8** 9**** confirmation (A)** undefined ( B)** Cancel (C)** Change Password button (D)** confirm the modifier key (E)** undefined (F)
Date : 2025-09-18 Size : 38kb User : 雷莲波

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