VHDL-FPGA-Verilog List Page 1896

VHDL-FPGA-Verilog list

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Xilinx Downloaded：0: Xilinx FPGA开发实用教程(121-180).rar
Date : 2025-09-18 Size : 11.35mb User : yinxiupu
cnt60 Downloaded：0: 60 binary counter (hexadecimal and decimal by a connection form)
Date : 2025-09-18 Size : 194kb User : 伍利衡
rel_08_done Downloaded：0: Modified from OpenCores Othello game code. Using the VGA output display, PS2 keyboard (W, A, S, D, Enter) input control to achieve AI, LED lights indicate whether the game is over, VGA display frequency of 25MHz, the sys
Date : 2025-09-18 Size : 247kb User : 诗律
VHDL-multi-function-clock Downloaded：0: a multi-function clock
Date : 2025-09-18 Size : 715kb User : Chaowei Liu
VHD_IIR Downloaded：0: VHDL-based IIR digital filters (infinite impulse response)
Date : 2025-09-18 Size : 567kb User : 祥子
DSP_FPGA Downloaded：0: Video Processing PDF
Date : 2025-09-18 Size : 141kb User : otto
Altera_I2C_example Downloaded：0: IIC VHDL
Date : 2025-09-18 Size : 2.41mb User : otto
bujindianji_28BYJ-48 Downloaded：0: With emu8086 working principle of stepper motor simulation and implementation features.
Date : 2025-09-18 Size : 112kb User : qianqinpeng
chufaqi Downloaded：0: EDA program design, implementation, signed five divider, includes all source code and class design report.
Date : 2025-09-18 Size : 501kb User :
dianpianjiyu41010 Downloaded：0: MCP41010 and SCM led brightness adjustment, blue LCD backlight control and regulation systems
Date : 2025-09-18 Size : 74kb User : 程鹏
lfp Downloaded：0: verilog HDL code of 8 eight-order low-pass filter input
Date : 2025-09-18 Size : 750kb User : liqihong
div Downloaded：0: QUSRTUS II environment, VHDL preparation. Divided by 2 divided by 4 divided by 8
Date : 2025-09-18 Size : 125kb User : vanessa

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