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VHDL-FPGA-Verilog list
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16* 16 dot matrix display program can be shaped to achieve the output font glyph transformation moves
Date : 2025-09-18 Size : 56kb User : 浅浅

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Digital clock function can be used with EDA time course experiment, alarm clock, can set their own time adjustment function
Date : 2025-09-18 Size : 631kb User : 浅浅

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EDA course experiment the basic counter and 16-bit counter cascade of simple 48-bit counter 96
Date : 2025-09-18 Size : 26kb User : 浅浅

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jk flip flop using vhdl, the different states in the jk flip flop is added, the coding which is used is very simple, thank you
Date : 2025-09-18 Size : 212kb User : Maddy

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I2C verilog IP, can be synthesized and fpga proven.
Date : 2025-09-18 Size : 683kb User : Jason

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This a use vhdl language 74LS160 counter with synchronous set, asynchronous clear function.
Date : 2025-09-18 Size : 38kb User :

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This a 138 using the VHDL language decoder, decoder 138 function as this will not go into details.
Date : 2025-09-18 Size : 25kb User :

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Using VHDL language and practical multi-mode display of water lights, it works hand-selectable frequencies, selectable display mode can be automatically switched manually.
Date : 2025-09-18 Size : 420kb User :

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Source code in hexadecimal display, consists of three modules: frequency, count, display. Vhdl for primary readers and college students
Date : 2025-09-18 Size : 4kb User : 刘海亮

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Written and practical use of VHDL in Happy Valley, it is working modes, selectable frequencies, the circuit can also automatically select.
Date : 2025-09-18 Size : 421kb User :

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Using vhdl write 8-bit full adder of the program, suitable for beginners to understand and master the VHDL written rules.
Date : 2025-09-18 Size : 110kb User :

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Written in VHDL with the use of the keyboard scanning process.
Date : 2025-09-18 Size : 2.15mb User :
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