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This article describes the design of a CIC filter based on the signal processing theory.Because of its structure only using the adder and the delay devices without multiplier,it is very suitable for FPGA to achieve the C
Date : 2025-09-17 Size : 324kb User : jiangtao

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An intersection traffic control system, its east and west in both directions in addition to red, yellow, green light indicating whether to allow access, but also has a clock to countdown display allows the passage of ti
Date : 2025-09-17 Size : 379kb User : patient sun

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bcd adder
Date : 2025-09-17 Size : 3kb User : 王小雨

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Using the FPGA Verilog programming language on the conversion of digital wireless communication function
Date : 2025-09-17 Size : 3kb User : 卫晓辉

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A file for Buit In self Test SELF TEST
Date : 2025-09-17 Size : 1kb User : sreeram a m

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This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth
Date : 2025-09-17 Size : 2kb User : 孙银龙

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The touch screen show touch coordinates
Date : 2025-09-17 Size : 19.03mb User : 郭菲菲

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With 16 V8R making a gate
Date : 2025-09-17 Size : 12kb User : ROBIN

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Based on VHDL language, write a 32-bit full adder files can be directly compile
Date : 2025-09-17 Size : 486kb User : zhang

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To achieve a video capture, 1 reverse data transmitter source, Using 8b10b code.
Date : 2025-09-17 Size : 101kb User : wzx

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tlk2201 transmitting and receiving source, 8b10b codec to achieve gigabit rate transceiver. Optical receiver can be used to transmit video processing strings and transform.
Date : 2025-09-17 Size : 1kb User : wzx

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Verilog DDS generator
Date : 2025-09-17 Size : 1.13mb User : fu
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