VHDL-FPGA-Verilog List Page 170

VHDL-FPGA-Verilog list

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add Downloaded：0: A full adder with quartus schematic input,
Date : 2025-05-20 Size : 1kb User : zhangning194
交通信号灯 Downloaded：0: Simulated traffic signal lamp.
Date : 2025-05-20 Size : 1.41mb User : 蜻鬼
uart Downloaded：0: Realize serial data sending and receiving with the computer terminal
Date : 2025-05-20 Size : 1kb User : hurricanhup
AdlER Downloaded：0: some thing is very off about this
Date : 2025-05-20 Size : 4.93mb User : Benten
spram Downloaded：0: Verilog written in spram, including the top-level module, control module and spram ontology, where spram is the IP kernel provided by Altera, has been running on quartus 16
Date : 2025-05-20 Size : 2.73mb User : keykai
bist 2017 paper Downloaded：0: A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorando
Date : 2025-05-20 Size : 1.5mb User : Maddy619
spec.tar Downloaded：0: M.2 testing specification
Date : 2025-05-20 Size : 444kb User : isaac172106
tengkan-V2.2 Downloaded：0: Calculation crosshairs diffraction image at different distances, Channelized receiver based on multi-phase structure, Verification is available.
Date : 2025-05-20 Size : 148kb User : manjaofienen
hhcit Downloaded：0: Includes the modulation, demodulation, signal to noise ratio calculation, Including AHP, factor analysis, regression analysis, cluster analysis, Noisy pulse correlation detection signal.
Date : 2025-05-20 Size : 148kb User : 张海涛
vtrb Downloaded：0: % disp('MATLAB encoder output') % disp(u)
Date : 2025-05-20 Size : 165kb User : Ravin48
basic_uart Downloaded：0: basic code for UART receiver and transmeter
Date : 2025-05-20 Size : 3kb User : Ravin48
RS232_verilog1 Downloaded：0: RS232 communication protocol Verilog program. After debugging can be used
Date : 2025-05-20 Size : 6.38mb User : 你好PSL

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