Verilog written in spram, including the top-level module, control module and spram ontology, where spram is the IP kernel provided by Altera, has been running on quartus 16

spram\db\altsyncram_1ei1.tdf
spram\db\altsyncram_34i1.tdf
spram\db\altsyncram_k3c1.tdf
spram\db\logic_util_heursitic.dat
spram\db\prev_cmp_spram_core.qmsg
spram\db\spram_core.ae.hdb
spram\db\spram_core.amm.cdb
spram\db\spram_core.asm.qmsg
spram\db\spram_core.asm.rdb
spram\db\spram_core.asm_labs.ddb
spram\db\spram_core.cbx.xml
spram\db\spram_core.cmp.bpm
spram\db\spram_core.cmp.cdb
spram\db\spram_core.cmp.hdb
spram\db\spram_core.cmp.kpt
spram\db\spram_core.cmp.logdb
spram\db\spram_core.cmp.rdb
spram\db\spram_core.cmp0.ddb
spram\db\spram_core.cmp1.ddb
spram\db\spram_core.cmp2.ddb
spram\db\spram_core.cmp_merge.kpt
spram\db\spram_core.db_info
spram\db\spram_core.eda.qmsg
spram\db\spram_core.fit.qmsg
spram\db\spram_core.hier_info
spram\db\spram_core.hif
spram\db\spram_core.idb.cdb
spram\db\spram_core.lpc.html
spram\db\spram_core.lpc.rdb
spram\db\spram_core.lpc.txt
spram\db\spram_core.map.bpm
spram\db\spram_core.map.cdb
spram\db\spram_core.map.hdb
spram\db\spram_core.map.kpt
spram\db\spram_core.map.logdb
spram\db\spram_core.map.qmsg
spram\db\spram_core.map_bb.cdb
spram\db\spram_core.map_bb.hdb
spram\db\spram_core.map_bb.logdb
spram\db\spram_core.pre_map.cdb
spram\db\spram_core.pre_map.hdb
spram\db\spram_core.rpp.qmsg
spram\db\spram_core.rtlv.hdb
spram\db\spram_core.rtlv_sg.cdb
spram\db\spram_core.rtlv_sg_swap.cdb
spram\db\spram_core.sgate.rvd
spram\db\spram_core.sgate_sm.rvd
spram\db\spram_core.sgdiff.cdb
spram\db\spram_core.sgdiff.hdb
spram\db\spram_core.sld_design_entry.sci
spram\db\spram_core.sld_design_entry_dsc.sci
spram\db\spram_core.smart_action.txt
spram\db\spram_core.sta.qmsg
spram\db\spram_core.sta.rdb
spram\db\spram_core.sta_cmp.8_slow.tdb
spram\db\spram_core.syn_hier_info
spram\db\spram_core.tis_db_list.ddb
spram\db\spram_core.tmw_info
spram\gene.v
spram\gene.v.bak
spram\greybox_tmp\cbx_args.txt
spram\incremental_db\compiled_partitions\spram_core.db_info
spram\incremental_db\compiled_partitions\spram_core.root_partition.cmp.cbp
spram\incremental_db\compiled_partitions\spram_core.root_partition.cmp.cdb
spram\incremental_db\compiled_partitions\spram_core.root_partition.cmp.dfp
spram\incremental_db\compiled_partitions\spram_core.root_partition.cmp.hdb
spram\incremental_db\compiled_partitions\spram_core.root_partition.cmp.kpt
spram\incremental_db\compiled_partitions\spram_core.root_partition.cmp.logdb
spram\incremental_db\compiled_partitions\spram_core.root_partition.cmp.rcfdb
spram\incremental_db\compiled_partitions\spram_core.root_partition.cmp.re.rcfdb
spram\incremental_db\compiled_partitions\spram_core.root_partition.map.cbp
spram\incremental_db\compiled_partitions\spram_core.root_partition.map.cdb
spram\incremental_db\compiled_partitions\spram_core.root_partition.map.dpi
spram\incremental_db\compiled_partitions\spram_core.root_partition.map.hdb
spram\incremental_db\compiled_partitions\spram_core.root_partition.map.kpt
spram\incremental_db\README
spram\quartus_nativelink_synthesis.log
spram\simulation\modelsim\modelsim.ini
spram\simulation\modelsim\msim_transcript
spram\simulation\modelsim\rtl_work\@_opt\vopt19qcf2
spram\simulation\modelsim\rtl_work\@_opt\vopt1rmag2
spram\simulation\modelsim\rtl_work\@_opt\vopt22jq4v
spram\simulation\modelsim\rtl_work\@_opt\vopt2t8k2y
spram\simulation\modelsim\rtl_work\@_opt\vopt33ssjs
spram\simulation\modelsim\rtl_work\@_opt\vopt48b6g2
spram\simulation\modelsim\rtl_work\@_opt\vopt5e0eww
spram\simulation\modelsim\rtl_work\@_opt\vopt5sc9f2
spram\simulation\modelsim\rtl_work\@_opt\vopt6ayh2y
spram\simulation\modelsim\rtl_work\@_opt\vopt6i8j4v
spram\simulation\modelsim\rtl_work\@_opt\vopt6jenjs
spram\simulation\modelsim\rtl_work\@_opt\vopt8926f2
spram\simulation\modelsim\rtl_work\@_opt\vopt8r03g2
spram\simulation\modelsim\rtl_work\@_opt\vopt9tje2y
spram\simulation\modelsim\rtl_work\@_opt\vopt9ymbww
spram\simulation\modelsim\rtl_work\@_opt\vopta2yg4v
spram\simulation\modelsim\rtl_work\@_opt\voptay9ja2
spram\simulation\modelsim\rtl_work\@_opt\voptb8n0g2
spram\simulation\modelsim\rtl_work\@_opt\voptceb8ww
spram\simulation\modelsim\rtl_work\@_opt\voptd2rdks
spram\simulation\modelsim\rtl_work\@_opt\voptda9a2y

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