VHDL-FPGA-Verilog List Page 1414

VHDL-FPGA-Verilog list

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divid Downloaded：0: Divided modeling based on VHDL, call the main division operation is used to shift data
Date : 2025-09-10 Size : 1kb User : 李佳伟
muti Downloaded：0: Multiplier algorithm based on VHDL modeling, used mainly for data shift
Date : 2025-09-10 Size : 3.35mb User : 李佳伟
LCD1602four Downloaded：0: msp430 to 553 LCD1602 program, the hope that useful.
Date : 2025-09-10 Size : 2kb User : 秦璐平
LED Downloaded：0: VHDL Control LED
Date : 2025-09-10 Size : 182kb User : gaojian
clock24 Downloaded：0: clk: the reference clock signal input sec_narmal: The cycle of the signal output 1s sec_s: The cycle of the signal output 0.5s sec_m: cycle 0.01s signal output sec_h: The cycle of the signal output 0.0005s
Date : 2025-09-10 Size : 952kb User : 田明
759744 Downloaded：0: dpll unit
Date : 2025-09-10 Size : 122kb User : taoyuan
my_uart Downloaded：0: Data transceiver, serial module, you can use the serial port to debug his assistant to send and receive data, verify the functionality of the module
Date : 2025-09-10 Size : 496kb User : 周勇涛
nios2_ucos2 Downloaded：0: Embedded Nios2 System based on Altera s FPGA, with uC/OS2 RTOS transplanted. Function included: 1602 character LCD display, 4*4 matrix keyboard detection based on interruption, LED flush lights.
Date : 2025-09-10 Size : 14.19mb User : 哲
miaobiao Downloaded：0: Stopwatch functions, from zero in mind to 99, you can pause, can be cleared.
Date : 2025-09-10 Size : 1.26mb User : supercheetah
rotary Downloaded：0: Rotary encoder verilog language program, you can identify the direction of rotation.
Date : 2025-09-10 Size : 1kb User : 梁
Cipher-lock.doc Downloaded：0: VHDL implementation of the four electronic locks, and 12864 on the LCD screen
Date : 2025-09-10 Size : 6kb User : 刘永
left_right_leds Downloaded：0: The rotary encoder VHDL driver, clever elimination of key noise.
Date : 2025-09-10 Size : 2kb User : 梁

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